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US 10,832,939 B2Granted
Semiconductor device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorHoon-Sung Choi
Life of this patent
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Abstract
A semiconductor comprises two transistors of the first conductivity type separated from two transistors of a second conductivity type by a first element isolation layer. Further, the two transistors of the first conductivity type are separated from each other by a second element isolation layer and the two transistors of the second conductivity type are separated from each other by a third element isolation layer. In example embodiments, the second and third element isolation layers are shallower than the first element isolation layer.
Claims19
A semiconductor device comprising:
- a substrate;
- a first impurity region of a first conductivity type on the substrate;
- a second impurity region of a second conductivity type on the substrate to be adjacent to the first impurity region;
- a first single semiconductor layer of the second conductivity type on the first impurity region;
- a second single semiconductor layer of the first conductivity type on the second impurity region;
- a first buried insulation layer on the first single semiconductor layer;
- a second buried insulation layer on the second single semiconductor layer;
- a third semiconductor layer on the first buried insulation layer;
- a fourth semiconductor layer on the second buried insulation layer;
- a first transistor and a second transistor on the first single semiconductor layer, respectively;
- a third transistor on the second single semiconductor layer;
- a first element isolation layer which separates the second transistor and the third transistor;
- and
- a second element isolation layer which separates the first transistor and the second transistor and is shallower than the first element isolation layer,
- wherein the first transistor and the second transistor share the first single semiconductor layer as a common body region.
12 more elements
A semiconductor device comprising:
- a substrate;
- a first impurity region of a first conductivity type and a second impurity region of a second conductivity type in contact with each other on the substrate;
- a first single semiconductor layer of the second conductivity type on the first impurity region;
- a second single semiconductor layer of the first conductivity type on the second impurity region;
- a buried insulation layer on the first single semiconductor layer and the second single semiconductor layer;
- a third semiconductor layer overlapping the first single semiconductor layer, and a fourth semiconductor layer overlapping the second single semiconductor layer on the buried insulation layer;
- a first element isolation layer in the third semiconductor layer;
- a first transistor and a second transistor on both sides of the first element isolation layer on the first single semiconductor layer;
- and
- a second element isolation layer which completely separates the first single semiconductor layer and the second single semiconductor layer,
- wherein the first transistor and the second transistor share the first single semiconductor layer as a common body region.
8 more elements
A semiconductor device comprising:
- a substrate;
- a first impurity region of a first conductivity type on the substrate;
- a second impurity region of a second conductivity type on the substrate to be adjacent to the first impurity region;
- a first single semiconductor layer of the second conductivity type on the first impurity region;
- a second single semiconductor layer of the first conductivity type on the second impurity region;
- a first buried insulation layer on the first single semiconductor layer;
- a second buried insulation layer on the second single semiconductor layer;
- a third semiconductor layer on the first buried insulation layer;
- a fourth semiconductor layer on the second buried insulation layer;
- a first transistor on the first single semiconductor layer;
- a second transistor on the second single semiconductor layer;
- a first element isolation layer which separates the first transistor and the second transistor;
- a second element isolation layer in the third semiconductor layer shallower than the first element isolation layer;
- and
- a first well contact connected to the first single semiconductor layer, the first well contact not between the first transistor and the first element isolation layer;
- and
- a third transistor on the first single semiconductor layer and separated by the first transistor and the second element isolation layer,
- wherein the first transistor and the third transistor share the first single semiconductor layer as a common body region.
15 more elements
Dependencies are inferred from the claim text.