US 10,832,916 B1Granted

Self-aligned gate isolation with asymmetric cut placement

AssigneeInternational Business Machines Corporation

InventorsRuilong Xie, Carl Radens, Kangguo Cheng, Veeraraghavan S. Basker

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Abstract

A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

Claims25

Dependent claims

A method of forming a semiconductor structure comprising:

forming a plurality of fins over a top surface of a substrate;
forming a shallow trench isolation region over the top surface of the substrate surrounding the plurality of fins;
forming a plurality of nanosheet stacks of channel material over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet field-effect transistors;
forming a channel protecting liner over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks formed over a first one of the plurality of fins, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks formed over a second one of the plurality of fins;
forming a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner;
forming at least one asymmetric self-aligned gate isolation structure over the channel protecting liner;
and
forming at least one symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third one of the plurality of fins and a fourth one of the plurality of fins.

5 more elements

A semiconductor structure comprising:

a substrate;
a plurality of fins disposed over a top surface of the substrate;
a shallow trench isolation region disposed over the top surface of the substrate surrounding the plurality of fins;
a plurality of nanosheet stacks of channel material disposed over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet field-effect transistors;
a channel protecting liner disposed over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks disposed over a first one of the plurality of fins, the channel protecting liner being further disposed over a portion of the shallow trench isolation region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks disposed over a second one of the plurality of fins;
a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner;
at least one asymmetric self-aligned gate isolation structure disposed over the channel protecting liner;
and
at least one symmetric self-aligned gate isolation structure disposed over a portion of the shallow trench isolation region between a third one of the plurality of fins and a fourth one of the plurality of fins.

6 more elements

An integrated circuit comprising:

a nanosheet field-effect transistor structure comprising:
a substrate;
a plurality of fins disposed over a top surface of the substrate;
a shallow trench isolation region disposed over the top surface of the substrate surrounding the plurality of fins;
a plurality of nanosheet stacks of channel material disposed over the plurality of fins, the plurality of nanosheet stacks providing channels for one or more nanosheet field-effect transistors;
a channel protecting liner disposed over at least a portion of sidewalls and a top surface of a first one of the plurality of nanosheet stacks disposed over a first one of the plurality of fins, the channel protecting liner being further disposed over a portion of the shallow trench isolation region extending from the portion of the sidewalls of the first nanosheet stack toward a second one of the plurality of nanosheet stacks disposed over a second one of the plurality of fins;
a plurality of gate stacks surrounding portions of the plurality of nanosheet stacks exposed by the channel protecting liner;
at least one asymmetric self-aligned gate isolation structure disposed over the channel protecting liner;
and
at least one symmetric self-aligned gate isolation structure disposed over a portion of the shallow trench isolation region between a third one of the plurality of fins and a fourth one of the plurality of fins.

7 more elements

Dependencies are inferred from the claim text.