Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance

A method for fabricating a semiconductor device, comprising:

• forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises:
• (i) a nanosheet stack structure comprising a stack of alternating semiconductor layers comprising a plurality of sacrificial nanosheet layers and a plurality of active nanosheet channel layers, wherein each active nanosheet channel layer is disposed between sacrificial nanosheet layers in the nanosheet stack structure;
• (ii) a dummy gate structure covering the nanosheet stack structure to define a gate region;
• and (iii) a gate sidewall spacer disposed on sidewalls of the dummy gate structure;
• laterally recessing exposed sidewall surfaces of the sacrificial nanosheet layers to form recessed regions within the sidewalls of the nanosheet stack structure, wherein the lateral recessing is performed by etching the sacrificial nanosheet layers selective to the active nanosheet channel layers;
• forming source/drain extension contacts on exposed end portions of the active nanosheet channel layers, wherein the source/drain extension contacts are formed on exposed surfaces of the active nanosheet channel layers within the recessed regions and on exposed sidewall surfaces of the active nanosheet channel layers;
• filling a remaining portion of the recessed regions with dielectric material to form embedded gate sidewall spacers;
• and
• forming source/drain layers in contact with the source/drain extension contacts;
• wherein the exposed sidewall surfaces of the sacrificial nanosheet layers are recessed to a recess depth which exposes portions of the active nanosheet channel layers overlapped by the dummy gate structure, which define a gate length of the field-effect transistor device, wherein the method further comprises:
• forming sacrificial inner spacers within the recessed regions to cover the exposed portions of the active nanosheet channel layers that define the gate length of the field-effect transistor device;
• and
• forming the source/drain extension contacts on the end portions of the active nanosheet channel layers after forming the sacrificial inner spacers within the recessed regions;
• wherein the sacrificial inner spacers prevent the source/drain extension contacts from being formed on the portions of the active nanosheet channel layers that define the gate length of the field-effect transistor device.

A method for fabricating a semiconductor device, comprising:

• forming a field-effect transistor device on a semiconductor substrate, wherein the field-effect transistor device comprises:
• (i) a nanosheet stack structure comprising a stack of alternating semiconductor layers comprising a plurality of sacrificial nanosheet layers and a plurality of active nanosheet channel layers, wherein each active nanosheet channel layer is disposed between sacrificial nanosheet layers in the nanosheet stack structure;
• (ii) a dummy gate structure covering the nanosheet stack structure to define a gate region;
• and (iii) a gate sidewall spacer disposed on sidewalls of the dummy gate structure;
• laterally recessing exposed sidewall surfaces of the sacrificial nanosheet layers to form recessed regions within the sidewalls of the nanosheet stack structure, wherein the lateral recessing is performed by etching the sacrificial nanosheet layers selective to the active nanosheet channel layers, wherein the recessed regions have a recess depth which exposes portions of the active nanosheet channel layers overlapped by the dummy gate structure, which define a gate length of the field-effect transistor device;
• forming sacrificial inner spacers within the recessed regions to cover the exposed portions of the active nanosheet channel layers that define the gate length of the field-effect transistor device;
• forming epitaxial source/drain extension contacts on exposed end portions of the active nanosheet channel layers, wherein the source/drain extension contacts are formed on exposed surfaces of the active nanosheet channel layers within the recessed regions and on exposed sidewall surfaces of the active nanosheet channel layers;
• filling a remaining portion of the recessed regions with dielectric material to form embedded gate sidewall spacers which are disposed adjacent to the sacrificial inner spacers;
• forming epitaxial source/drain layers in contact with the epitaxial source/drain extension contacts;
• selectively removing the dummy gate structure to open the gate region and expose the nanosheet stack structure and the sacrificial inner spacers within the gate region;
• selectively removing the sacrificial nanosheet layers exposed in the gate region to release the active nanosheet channel layers and form spaces between the active nanosheet channel layers;
• selectively removing the sacrificial inner spacers within the spaces between the active channel layers, wherein the sacrificial inner spacers are formed of a material that has an etch selectivity with respect to materials of the sacrificial nanosheet layers, the active nanosheet channel layers, the embedded gate sidewall spacers, and the source/drain extension contacts;
• and
• forming a high-k dielectric/metal gate structure within the gate region to surround the active nanosheet channel layers;
• wherein the source/drain extension contacts are disposed between the embedded gate sidewall spacers and the active nanosheet channel layers, and extend from source/drain layers to the high-k dielectric/metal gate structure.