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US 10,832,793 B2Granted
Defective memory cell detection circuitry including use in automotive control systems
AssigneeMicron Technology, Inc.
InventorChristopher S. Johnson
Life of this patent
Estimating the term…
Abstract
In some examples, a defective memory cell detection circuitry is configured to provide a failure signal indicative of a failure of a sub-group of memory cells (e.g., a row of memory cells). The failure signal is generated responsive to the failure of a sense line to transition to one of a set of reference voltages within a threshold time from a memory command. In some examples, failure signals indicative of a failure of a sub-group of memory cells is used by vehicle computer control systems to operate a vehicle.
Claims25
An apparatus comprising:
- memory cells including a sub-group of the memory cells coupled to an access line;
- pairs of sense lines, each respective pair of sense lines coupled to a respective memory cell in the sub-group of the memory cells;
- sense amplifiers, each respective sense amplifier coupled to a respective pair of sense lines, each sense amplifier configured to sense data read from at least a selected one of the memory cells of the sub-group of memory cells;
- and
- defective memory cell detection circuitry coupled to at least one of the sense amplifiers and configured to provide a failure signal responsive to detection of a failure of at least one of the respective pair of sense lines coupled to the sense amplifier, the failure signal indicative of a defect affecting multiple ones of the memory cells in the sub-group of the memory cells.
2 more elements
A method comprising:
- activating a sub-group of memory cells using an access line coupled to the sub-group of memory cells;
- monitoring pairs of sense lines coupled to individual ones of the sub-group of memory cells via a sense amplifier associated with the pairs of sense lines;
- and
- providing a failure signal responsive to a voltage on at least one of the pairs of sense lines failing to reach one of a plurality of reference voltages a threshold time after said activating.
1 more element
A system comprising:
- memory including a plurality of memory cells each coupled to one or more sense lines;
- defective memory cell detection circuitry coupled to the memory and configured to provide a failure signal indicative of a defect affecting a sub-group of memory cells of the memory by determining a failure on the one or more sense lines of at least a memory cell of the plurality of memory cells responsive to a read or write command;
- a memory controller coupled to the defective memory cell detection circuitry, the memory controller configured to provide the read or write command and receive the failure signal from the defective memory cell detection circuitry;
- and
- a vehicle computer control system coupled to the memory controller, the vehicle computer control system configured to utilize data stored in the memory to at least partially, control an automobile.
2 more elements
A system comprising:
- memory;
- defective memory cell detection circuitry coupled to the memory and configured to provide a failure signal indicative of a defect affecting a sub-group of memory cells of the memory;
- a memory controller coupled to the defective memory cell detection circuitry, the memory controller configured to receive the failure signal;
- and
- a vehicle computer control system coupled to the memory controller, the vehicle computer control system configured to utilize data stored in the memory to at least partially control a vehicle, wherein the automotive control system is further configured to change a speed or heading of the vehicle responsive to the failure signal.
2 more elements
Dependencies are inferred from the claim text.