US 10,832,789 B1Granted

System countermeasure for read operation during TLC program suspend causing ADL data reset with XDL data

AssigneeWestern Digital Technologies, Inc.

InventorsMahim Gupta, Rohan Dhekane, Aaron Lee

Life of this patent

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Abstract

Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die, the programming operation including populating a transfer data latch with a first set of data and transferring the data to a first data latch, populating the transfer data latch with a second set of data and transferring the data to second data latch, arranging the first and second data sets in a suitable format of the multi-state block, and writing the data sets to the multi-state block; prior to populating the transfer data latch with the second data set, performing a program suspend and read operation thereby populating the transfer data latch with read data; and comparing the read data to the data contained in the first data latch and, if the comparison results in a match, identifying the subject die as faulty.

Claims20

Dependent claims

A method for identifying a faulty memory die in a non-volatile memory storage system, comprising:

commencing a programming operation of a multi-state block of a subject memory die, wherein the multi-state block includes a transfer data latch (XDL) and at least a first data latch and a second data latch, the programming operation comprising:
populating the transfer data latch (XDL) with a first set of data and transferring the first set of data to the first data latch;
populating the transfer data latch (XDL) with a second set of data and transferring the second set of data to the second data latch;
arranging the first and second sets of data in a suitable format of the multi-state block;
and
writing the first and second sets of data to the multi-state block;
performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before the populating of the transfer data latch (XDL) with the second set of data, thereby populating the transfer data latch (XDL) with a set of read data;
comparing the read data contained in the transfer data latch (XDL) and the data contained in the first data latch;
and
if the data contained in the first data latch matches the read data, identifying the subject memory die as faulty.

7 more elements

A memory controller, comprising:

a first port configured to couple to a memory array, the memory array comprising at least one subject memory die having a multi-state block, wherein the multi-state block includes a transfer data latch (XDL) and at least a first data latch and a second data latch;
the memory controller configured to:
transmit a program command to the multi-state block to:
populate the transfer data latch (XDL) with a first set of data and transfer the first set of data to the first data latch;
populate the transfer data latch (XDL) with a second set of data and transfer the second set of data to the second data latch;
arrange the first and second sets of data in a suitable format of the multi-state block;
and
write the first and second sets of data to the multi-state block;
transmit a program suspend and read command after the first set of data is transferred to the first data latch and before the transfer data latch (XDL) is populated with the second set of data, thereby populating the transfer data latch (XDL) with a set of read data;
compare the read data contained in the transfer data latch (XDL) and the data contained in the first data latch;
and
identify the subject memory die as faulty if the data contained in the first data latch matches the read data.

9 more elements

A non-volatile memory system, configured to identify a faulty memory die thereof, comprising:

a memory array storing data in a multi-state block of a subject memory die of the memory array, wherein the multi-state block is programmed using a transfer data latch (XDL) and at least a first data latch and a second data latch;
and
a controller coupled to the memory array, wherein the controller is configured to:
transmit a program command to the multi-state block to:
populate the transfer data latch (XDL) with a first set of data and transfer the first set of data to the first data latch;
populate the transfer data latch (XDL) with a second set of data and transfer the second set of data to the second data latch;
arrange the first and second sets of data in a suitable format of the multi-state block;
and
write the first and second sets of data to the multi-state block;
transmit a program suspend and read command after the first set of data is transferred to the first data latch and before the transfer data latch (XDL) is populated with the second set of data, thereby populating the transfer data latch (XDL) with a set of read data;
compare the read data contained in the transfer data latch (XDL) and the data contained in the first data latch;
and
identify the subject memory die as faulty if the data contained in the first data latch matches the read data.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/440,018Filed 13 Jun 2019
Granted: 10 Nov 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G11C 29/38
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: response verification devices
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits