Semiconductor device
AssigneeRenesas Electronics Corporation
InventorYuichiro Ishii
Life of this patent
Estimating the term…
Abstract
A semiconductor device has a memory circuit and a logic circuit coupled with a memory circuit. the memory circuit included a memory array in which memory cells are arranged in a matrix, an input/output circuit for writing data to the memory cells and reading data from the memory cells, and a control circuit for generating a control signal for controlling the input/output circuit. In a test operation for testing the logic circuit, the input/output circuit receives a test data. The control circuit raises and lowers the control signal based on a rising and a falling of an external clock signal, thereby the test data is output to the logic circuit via the input/output circuit.
Claims20
A semiconductor device comprising:
- a memory circuit;
- and
- a logic circuit coupled with the memory circuit,
- wherein the memory circuit includes:
- a memory array including a plurality of memory cells arranged in a matrix;
- an input/output circuit for writing data to the plurality of memory cells and reading data from the plurality of memory cells;
- and
- a control circuit for generating a control signal for controlling the input/output circuit,
- wherein in a first test operation for testing the logic circuit, the control circuit receives an external clock signal, raises the control signal based on a rising of the external clock signal and lowers the control signal based on a falling of the external clock signal,
- wherein in the first test operation, the input/output circuit receives a test data, and
- wherein in the first test operation, the input/output circuit outputs to the test data to the logic circuit based on the rising and falling of the control circuit.
A semiconductor device comprising:
- a memory circuit including a memory array including a plurality of memory cells arranged in a matrix, a plurality of input/output circuits for writing data to the plurality of memory cells and reading data from the plurality of memory cells, and a control circuit for generating a control signal for controlling the plurality of input/output circuits;
- and
- a plurality of logic circuits coupled with the plurality of input/output circuits,
- wherein in a test operation for testing the plurality of logic circuits, the control circuit receives an external clock signal and generates the control signal synchronized with a pulse width of the external clock signal,
- wherein in the test operation, each of the plurality of input/output circuits receives a test data, and outputs the test data to each of the plurality of logic circuits based on the control signal.
A semiconductor device comprising:
- a memory circuit;
- and
- a logic circuit coupled with the memory circuit,
- wherein the memory circuit includes:
- a memory array including a plurality of memory cells arranged in a matrix;
- an input/output circuit for writing data to the plurality of memory cells and reading data from the plurality of memory cells;
- and
- a control circuit for generating a control signal for controlling the input/output circuit,
- wherein in a test operation for testing the logic circuit, the control circuit receives an external clock signal and generates a control signal synchronized with a pulse width of the external clock signal,
- wherein in the first test operation, the input/output circuit receives a test data and outputs the test data to the logic circuit based on the control circuit.
Dependencies are inferred from the claim text.