Semiconductor storage device

A semiconductor storage device comprising:

• a plurality of memory cell transistors above a semiconductor substrate, including first, second, third, and fourth groups of memory cell transistors, wherein the first and second groups of memory cell transistors are respectively at opposite sides of a first group of semiconductor pillars spaced apart and aligned along a first direction, and the third and fourth groups of memory cell transistors are respectively at opposite sides of a second group of semiconductor pillars spaced apart and aligned along the first direction, and the first group of semiconductor pillars is spaced apart from the second group of semiconductor pillars in a second direction crossing the first direction;
• a plurality of word lines stacked above the semiconductor substrate, including first and second word lines at a same level above the semiconductor substrate, wherein the first word line is connected to gates of the memory cell transistors in the first and third groups of memory cell transistors and the second word line is connected to gates of the memory cell transistors in the second and fourth groups of memory cell transistors;
• and
• a controller configured to perform a write operation per group of memory cell transistors connected to one word line, wherein
• during a write operation performed on the third group of memory cell transistors connected to the first word line, the controller determines an initial program voltage to be applied to the first word line on the basis of a first number of loops, which is determined during the write operation performed on the first group of memory cell transistors connected to the first word line, and
• during a write operation performed on the fourth group of memory cell transistors connected to the second word line, the controller determines an initial program voltage to be applied to the second word line on the basis of a second number of loops, which is determined during the write operation performed on the second group of memory cell transistors connected to the second word line.

A method of performing a write operation on a semiconductor storage device comprising a plurality of memory cell transistors above a semiconductor substrate, including first, second, third, and fourth memory cell transistors, wherein the first and second memory cell transistors are at opposite sides of a first semiconductor body in which channel regions of the first and second memory cell transistors are located, and third and fourth memory cell transistors are at opposite sides of a second semiconductor body in which channel regions of the third and fourth memory cell transistors are located, and a plurality of word lines including a first word line connected to gates of the first and third memory cell transistors, and a second word line connected to gates of the second and fourth memory cell transistors, said method comprising:

• executing a write operation on the first memory cell transistor and then executing a write operation on the third memory cell transistor;
• and
• executing a write operation on the second memory cell transistor and then executing a write operation on the fourth memory cell transistor, wherein
• during the write operation performed on the third memory cell transistor, an initial program voltage applied to the first word line is set on the basis of a first number of loops, which is determined during the write operation performed on the first memory cell transistor, and
• during the program operation performed on the fourth memory cell transistor, an initial program voltage applied to the second word line is set on the basis of a second number of loops, which is determined during the write operation performed on the second memory cell transistor.