Integrated circuit device
AssigneeSamsung Electronics Co., Ltd.
InventorsJang-Gn Yun, Jae-Duk Lee
Life of this patent
Estimating the term…
Abstract
An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.
Claims20
An integrated circuit device comprising:
- a plurality of channel structures extending in a vertical direction from a main surface of a substrate;
- a plurality of memory cell strings disposed in the vertical direction along the plurality of channel structures, wherein each memory cell string includes a plurality of serially-connected memory cells;
- a plurality of gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines;
- and
- a plurality of driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines,
- wherein at least two gate lines spaced apart from one another in a horizontal direction with respect to the main surface of the substrate among the plurality of gate lines are commonly connected to one of the plurality of driving transistors.
An integrated circuit device comprising:
- channel structures extending in a vertical direction from a substrate;
- bit lines respectively connected to the channel structures and extending in a first horizontal direction;
- gate electrodes vertically stacked on the substrate, intersecting the channel structures, having a stepped pattern, and extending in a second horizontal direction over the substrate;
- and
- an erase control driving transistor and at least two string selection driving transistors,
- wherein at least two of the gate electrodes respectively function as erase control lines, at least another two of the gate electrodes respectively function as string selection lines, the erase control lines and the string selection lines are spaced apart from one another in the first horizontal direction, the erase control lines are commonly connected to the erase control driving transistor, and each of the string selection lines is respectively connected to one of the at least two string selection driving transistors.
An integrated circuit device comprising:
- channel structures extending in a vertical direction from a substrate;
- memory cell strings disposed in the vertical direction along the channel structures, wherein each one of the memory cell strings includes serially-connected memory cells;
- gate electrodes spaced apart from one another in the vertical direction, intersecting the channel structures, and extending in a second horizontal direction over the substrate;
- and
- driving transistors including erase control driving transistors and string selection driving transistors,
- wherein the gate electrodes include word lines, erase control lines, and string selection lines,
- the at least two of the erase control lines are spaced apart from one another in a first horizontal direction and are commonly connected to one erase control driving transistor, and
- the at least two string selection lines are spaced apart from one another in the first horizontal direction and are respectively connected to the at least two string selection driving transistors.
Dependencies are inferred from the claim text.