Negative voltage wordline methods and systems

A method for non-volatile memory, comprising:

• issuing a program command to control a bitline associated with a memory cell connected to an even selected wordline;
• driving odd non-selected wordlines, which are sequential and adjacent to the selected wordline and are capacitively coupled to the even selected wordline, to a pass voltage, thereby stepping the even selected wordline to a program voltage;
• returning the odd non-selected wordlines and the even selected wordline to zero volts;
• boosting the odd non-selected wordlines to a first positive voltage;
• holding the even selected wordline at zero volts;
• floating the even selected wordline;
• and
• during a soft erase operation, shifting the even selected wordline to less than zero volts due to capacitance effects by driving at least one of the odd non-selected wordlines to a voltage lower than the first positive voltage, thereby accelerating charge loss in a defective memory cell connected to the even selected wordline.

A non-volatile memory, comprising:

• a plurality of even wordlines;
• a plurality of odd wordlines alternating with ones of the plurality of even wordlines;
• a plurality of memory cells in a vertical stack connected to the plurality of even wordlines and the plurality of odd wordlines;
• a bit line connected at one end of the vertical stack of memory cells;
• and
• controller circuitry configured to issue signals thereby:
• boosting a non-selected wordline to a first positive voltage;
• holding a selected wordline at zero volts, the selected wordline being adjacent to the non-selected wordline and being capacitively coupled to the non-selected wordline;
• floating the selected wordline;
• and
• during a soft erase operation, shifting the selected wordline to a negative voltage due to capacitance effects by driving the non-selected wordline to a voltage lower than the first positive voltage, thereby
• accelerating charge loss in a defective memory cell connected to the selected wordline.

A non-volatile memory, comprising

• a plurality of even wordlines;
• a plurality of odd wordlines alternating with ones of the plurality of even wordlines;
• a plurality of memory cells in a vertical stack connected to the plurality of even wordlines and the plurality of odd wordlines;
• a bit line connected at one end of the vertical stack of memory cells;
• and
• controller circuitry configured to issue signals thereby:
• issuing a program command to control a bitline associated with s memory cell connected to an even selected wordline,
• driving odd non-selected wordlines, which are sequential and adjacent to the selected wordline and are capacitively coupled to the even selected wordline, to a pass voltage, thereby stepping
• the even selected wordline to a program voltage,
• returning the odd non-selected wordlines and the even selected wordline to zero volts,
• boosting the odd non-selected wordlines to a first positive voltage,
• holding the even selected wordline at zero volts,
• floating the even selected wordline, and
• during a soft erase operation, shifting the even selected wordline to less than zero volts due to capacitance effects by driving at least one of the odd non-selected wordlines to a voltage lower than the first positive voltage, thereby accelerating charge loss in a defective memory cell connected to the even selected wordline.