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US 10,832,776 B2Granted
Semiconductor device and semiconductor memory device
AssigneeToshiba Memory Corporation
InventorTetsuaki Utsumi
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes: a semiconductor substrate; a plurality of transistors provided on a surface of the semiconductor substrate; and a first circuit electrically connected to gate electrodes of the plurality of transistors. The plurality of transistors include: a first transistor and a second transistor that are adjacent via an insulating region in a first direction; a third transistor that is adjacent to the first transistor and the second transistor via the insulating region in a second direction intersecting the first direction; and a fourth transistor that is adjacent to the first transistor and the second transistor via the insulating region in the second direction. The first circuit sets the first through fourth transistors to an ON state according to a first signal.
Claims17
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of transistors provided on a surface of the semiconductor substrate;
- and
- a first circuit electrically connected to gate electrodes of the plurality of transistors,
- the plurality of transistors including:
- a first transistor and a second transistor that are adjacent via an insulating region in a first direction;
- a third transistor that is adjacent to the first transistor and the second transistor via the insulating region in a second direction intersecting the first direction;
- and
- a fourth transistor that is adjacent to the first transistor and the second transistor via the insulating region in the second direction,
- the first circuit
- setting the first through fourth transistors to an ON state according to a first signal,
- wherein the plurality of transistors include:
- a fifth transistor that comprises a region common to the second transistor;
- a sixth transistor that is adjacent to the fifth transistor via the insulating region in the first direction;
- a seventh transistor that is adjacent to the fifth transistor and the sixth transistor via the insulating region in the second direction;
- and
- an eighth transistor that is adjacent to the fifth transistor and the sixth transistor via the insulating region in the second direction, and
- the first circuit
- sets the fifth through eighth transistors to an OFF state according to the first signal, and
- sets the fifth through eighth transistors to an ON state according to a second signal.
17 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- first through fourth conductive layers aligned in a first direction intersecting a surface of the semiconductor substrate;
- a first semiconductor column extending in the first direction and facing the first through fourth conductive layers;
- a first insulating film provided between the first through fourth conductive layers and the first semiconductor column;
- and
- a plurality of transistors provided on the surface of the semiconductor substrate,
- the plurality of transistors comprising:
- a first transistor that is electrically connected to the first conductive layer;
- a second transistor that is electrically connected to the second conductive layer and is adjacent to the first transistor via an insulating region in a second direction intersecting the first direction;
- a third transistor that is electrically connected to the third conductive layer and is adjacent to the first transistor and the second transistor via the insulating region in a third direction intersecting the first direction and the second direction;
- and
- a fourth transistor that is electrically connected to the fourth conductive layer and is adjacent to the first transistor and the second transistor via the insulating region in the third direction.
9 more elements
A semiconductor memory device comprising:
- a semiconductor substrate;
- a first memory block and a second memory block that are provided separated from the semiconductor substrate in a first direction intersecting a surface of the semiconductor substrate, and are aligned in a second direction intersecting the first direction;
- and
- a plurality of transistors that are provided on the surface of the semiconductor substrate, and are aligned in a third direction intersecting the first direction and the second direction,
- the first memory block comprising:
- a plurality of first conductive layers aligned in the first direction;
- a first semiconductor column extending in the first direction and facing the plurality of first conductive layers;
- and
- a first insulating film provided between the plurality of first conductive layers and the first semiconductor column,
- the second memory block comprising:
- a plurality of second conductive layers aligned in the first direction;
- a second semiconductor column extending in the first direction and facing the plurality of second conductive layers;
- and
- a second insulating film provided between the plurality of second conductive layers and the second semiconductor column, and
- the plurality of transistors including:
- a first transistor that is electrically connected to one of the plurality of first conductive layers;
- a second transistor that is electrically connected to one of the plurality of second conductive layers;
- a third transistor that is electrically connected to one of the plurality of first conductive layers and is provided between the first transistor and the second transistor;
- and
- a fourth transistor that is electrically connected to one of the plurality of second conductive layers and is provided between the first transistor and the third transistor.
17 more elements
Dependencies are inferred from the claim text.