Variation resistant 3T3R binary weight cell with low output current and high on/off ratio
AssigneeSamsung Electronics Co., Ltd.
InventorsRyan M. Hatcher, Titash Rakshit, Jorge Kittl, Rwik Sengupta, Dharmendar Palle, Joon Goo Hong
Life of this patent
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Abstract
A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.
Claims20
A weight cell, comprising:
- a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET;
- a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET,
- a third FET;
- and
- a load resistor connected to a drain of the third FET,
- wherein an input to a source of the first FET includes a first programming voltage and an input to a source of the second FET includes a second programming voltage opposite of the first programming voltage such that a current output from a source of the third FET indicates a logical weight of the weight cell.
A device, comprising:
- an array of weight cells, each weight cell including:
- a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET;
- a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET,
- a third FET;
- and
- a load resistor connected to a drain of the third FET;
- and
- a processor configured to perform inference with the array of weight cells by:
- setting inputs for a row of weight cells from among the array of weight cells according to a logical value of a corresponding neuron;
- and
- reading outputs of a column of weight cells from among the array of weight cells.
A device, comprising:
- an array of weight cells, each weight cell including:
- a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET;
- a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET,
- a third FET;
- and
- a load resistor connected to a drain of the third FET;
- wherein an input to a source of the first FET includes a first programming voltage and an input to a source of the second FET includes a second programming voltage opposite of the first programming voltage such that a current output from a source of the third FET indicates a logical weight of the weight cell;
- and
- a processor configured to write to the resistive memory elements according to a direction of a current supplied to the resistive memory elements.
Dependencies are inferred from the claim text.