Architecture for enabling zero value shifting

A system comprising:

• an analog memory architecture for performing differential reading, including:
• a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, wherein the first cross-point devices converge at respective symmetry points;
• a first voltage pulse generator connected to the set of conductive row wires in the weight array;
• a second voltage pulse generator connected to the set of conductive column wires in the weight array;
• an analog-to-digital converter (ADC) connected, via an integrator, to the set of conductive column wires in the weight array;
• and
• a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires;
• the second cross-point devices including differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.

A method comprising:

• applying voltage pulses to first cross-point devices of a weight array of an analog memory architecture for performing differential reading to achieve symmetry point convergence, the first cross-point devices being located at intersections of a first set of conductive column wires and a first set of conductive row wires;
• copying conductance values for each of the first cross-point devices to a reference array of the analog memory architecture operatively coupled to the weight array, the reference array including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires, wherein the second cross-point devices include differential unipolar switching memory devices;
• and
• enabling zero-value shifting of the outputs of the first cross-point devices using the second cross-point devices.