Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorTakayuki Miyazaki
Life of this patent
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Abstract
A semiconductor memory device includes a first transistor connected between a high voltage line connected to a first end of a memory element and a first power supply terminal, and a second transistor connected between the high voltage line and a second power supply terminal, a third transistor connected between a low voltage line connected to a second end of the memory element and a third power supply terminal, and a fourth transistor connected between the low voltage line and a fourth power supply terminal. The second and fourth transistors satisfy the condition: |Vth|<|VG−VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate and a source or drain thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode current flows.
Claims20
A semiconductor memory device comprising:
- a first selection circuit including a first MOS transistor having a first terminal connected to a high voltage line that is connected to a first end of a two-terminal memory element and a second terminal connected to a first power supply voltage terminal, and a second MOS transistor having a first terminal connected to the high voltage line and a second terminal connected to a second power supply voltage terminal;
- and
- a second selection circuit including a third MOS transistor having a first terminal connected to a low voltage line that is connected to a second end of the two-terminal memory element and a second terminal connected to a third power supply voltage terminal and a fourth MOS transistor having a first terminal connected to the low voltage line and a second terminal connected to a fourth power supply voltage terminal,
- wherein each of the second and fourth MOS transistors satisfy the condition of |Vth|<|VG−VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate thereof and the second terminal thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode that is between the body thereof and the first terminal thereof is turned on.
A semiconductor memory device comprising:
- a first selection circuit including a first MOS transistor having a first terminal connected to a high voltage line that is connected to a first end of a two-terminal memory element and a second terminal connected to a first power supply voltage terminal, and a second MOS transistor having a first terminal connected to the high voltage line and a second terminal connected to a second power supply voltage terminal;
- a second selection circuit including a third MOS transistor having a first terminal connected to a low voltage line that is connected to a second end of the two-terminal memory element and a second terminal connected to a third power supply voltage terminal and a fourth MOS transistor having a first terminal connected to the low voltage line and a second terminal connected to a fourth power supply voltage terminal;
- a power supply circuit configured to generate first and second voltages and apply the first and second voltages to the first and second power supply voltage terminals, respectively, and generate third and fourth voltages and apply the third and fourth voltages to the third and fourth power supply voltage terminals, respectively;
- and
- a control circuit configured to control the first, second, third, and fourth transistors during a read operation or a write operation performed on the memory element, wherein
- each of the second and fourth MOS transistors satisfy the condition of |Vth|<|VG−VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate thereof and the second terminal thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode that is between the body thereof and the first terminal thereof is turned on.
A method of transitioning a memory element of a semiconductor memory device from a selected state to a non-selected state, wherein the semiconductor memory device includes:
- a first selection circuit including a first MOS transistor having a first terminal connected to a high voltage line that is connected to a first end of the memory element and a second terminal connected to a first power supply voltage terminal, and a second MOS transistor having a first terminal connected to the high voltage line and a second terminal connected to a second power supply voltage terminal;
- and
- a second selection circuit including a third MOS transistor having a first terminal connected to a low voltage line that is connected to a second end of the memory element and a second terminal connected to a third power supply voltage terminal and a fourth MOS transistor having a first terminal connected to the low voltage line and a second terminal connected to a fourth power supply voltage terminal,
- said method comprising:
- selecting the memory element by turning on the first and third transistors and turning off the second and fourth transistors;
- while the second and fourth transistors are turned off, turning off the first and third transistors at different timings to cause a parasitic diode current to be generated in a body of one of the second and fourth transistors;
- and
- while blocking the parasitic diode current that is generated in the body of said one of the second and fourth transistors from flowing to the second terminal of said one of the second and fourth transistors, transitioning the memory element to the non-selected state by turning on the second and fourth transistors.
Dependencies are inferred from the claim text.