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US 10,832,770 B2Granted
Single pulse memory operation
AssigneeSanDisk Technologies LLC
InventorsAli Al-Shamma, Yadhu Vamshi Vancha, Jeffrey Lee
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, methods, and computer program products are disclosed for a single pulse memory operation. An electrical source is configured to generate an electrical pulse. A selector for a memory cell is configured to conduct an electrical pulse from an electrical source to a memory cell in response to the electrical pulse exceeding a threshold. A control circuit is configured to maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.
Claims19
An apparatus comprising:
- a bit line;
- a word line;
- a memory cell connected between the bit line the word line;
- one or more electrical sources configured to generate and apply an electrical pulse to the word line and the bit line;
- a selector connected in series with the memory cell between the bit line and the word line, the selector configured to conduct the electrical pulse from the one or more electrical sources to the memory cell in response to the electrical pulse exceeding a threshold;
- and
- a control circuit connected to the one or more electrical sources and configured to control the one or more electrical sources to provide an initial spike for the pulse and subsequently maintain at least an operational level for the electrical pulse for a predefined time period to perform an operation on the memory cell.
4 more elements
A system comprising:
- an array comprising a plurality of phase change memory cells each having a reset amorphous state and a set crystalline state;
- a plurality of ovonic threshold switching (OTS) selectors, each of the OTS selectors positioned between a corresponding one of the phase change memory cells and electrical lines of the array;
- and
- an on-die controller configured to supply a reset current to one of the electrical lines associated with at least one of the phase change memory cells, the reset current including an initial spike activating at least one of the OTS selectors and resetting at least one of the phase change memory cells to the reset amorphous state without the reset current falling below a reset current threshold.
1 more element
An apparatus comprising:
- a bit line;
- a word line;
- a memory cell connected between the bit line and word line;
- a memory cell selector connected in series with the memory cell between the bit line and the word line;
- means for popping the memory cell selector with an operation current between the bit line and the word line such that the memory cell selector becomes conductive;
- means for setting a timer in response to the memory cell selector popping;
- means for supplying the operation current for at least a predefined time period based on the timer to perform an operation on the memory cell with the operation current;
- and
- means for detecting the memory cell selector popping by detecting a first crossing of an electrical spike threshold by the operation current and a second crossing of the electrical spike threshold by the operation current.
6 more elements
Dependencies are inferred from the claim text.