Program verification time reduction in non-volatile memory devices

A method, comprising:

• performing a program operation to program a memory cell of an array to a program voltage level, wherein the program voltage level is one of a plurality of program voltage levels to be programmed into the array;
• and
• performing a verification operation by applying a shared verify voltage level to the array to verify that the memory cell is programmed to the program voltage level, wherein the shared verify voltage level is a single verification voltage applied to a selected wordline (WL) of a first memory cell and a second memory cell and is used to verify at least two consecutive program voltage levels of the plurality of program voltage levels, and wherein the program voltage level is one of two consecutive program voltage levels of the plurality of program voltage levels to be verified by application of the shared verify voltage level;
• and
• wherein performing the verification operation using the shared verify voltage level includes comparing a first bitline (BL) current of the first memory cell to a first reference BL current and a second BL current of the second memory cell to a second reference BL current to verify that the first memory cell and second memory cell are programmed to a respective first program voltage level and second program voltage level of the two consecutive program voltage levels.

A system, comprising:

• a memory device;
• a memory controller coupled to the memory device, wherein the memory controller is to:
• perform a program operation to program a memory cell of an array of the memory device to a program voltage level, wherein the program voltage level is one of a plurality of program voltage levels to be programmed into the array;
• and
• perform a verification operation by applying a shared verify voltage level to the array to verify that the memory cell is programmed to the program voltage level, wherein the shared verify voltage level is a single verification voltage applied to a selected wordline (WL) of a first memory cell and a second memory cell and is to verify at least two consecutive program voltage levels of the plurality of program voltage levels, and wherein the program voltage level is one of two consecutive program voltage levels of the plurality of program voltage levels to be verified by application of the shared verify voltage level;
• and
• wherein control circuitry comprises sense circuitry to compare a first bitline (BL) current of the first memory cell to a first reference BL current and a second BL current of the second memory cell to a second reference BL current to verify that the first and second memory cells are programmed to a respective consecutive first program voltage level and a second program voltage level.