Variation tolerant read assist circuit for SRAM

A memory system, comprising:

• a plurality memory cells, each memory cell including:
• a bi-stable latch that stores a logic state;
• and
• a pass transistor coupled between the bi-stable latch and a bit line, wherein the pass transistor is configured to selectively output the logic state to the bit line responsive to a write line voltage that controls the pass transistor;
• and
• a read assist circuit configured to provide a plurality of write line voltages on a plurality of write lines, each write line connected to a gate of a corresponding pass transistor of a corresponding memory cell of the plurality of memory cells, the read assist circuit including:
• a voltage divider circuit, responsive to a master enable signal, and configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit responsive to read assist being enabled by the master enable signal;
• and
• a plurality of write line driver circuits corresponding to the plurality of memory cells, each write line driver circuit configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line of the plurality of write lines according to a corresponding individual enable signal that controls the each write line driver circuit.

A method of providing read assistance during a read operation to a plurality of memory cells, the method comprising:

• receiving a master enable signal;
• determining whether the master enable signal indicates read assistance is available for the plurality of memory cells;
• voltage dividing a power supply voltage to generate a source write line voltage responsive to determining that read assistance is available for the plurality of memory cells;
• generating one or more write line voltages based on the source write line voltage for a subset of the plurality of memory cells according to corresponding individual enable signals associated with the subset of the plurality of memory cells;
• and
• applying the one or more write line voltages to the subset of the plurality of memory cells that are enabled for read assistance during the read operation based on the corresponding individual enable signals,
• wherein the source write line voltage is a percentage of the power supply voltage, the percentage determined by a ratio of a first resistance of a first transistor compared to a second resistance of a second transistor of a voltage divider circuit that performs the voltage dividing.