Global bit line latch performance and power optimization
AssigneeInternational Business Machines Corporation
InventorsMartin Bernhard Schmidt, Harry Barowski, Alexander Fritsch, Matthias Hock
Life of this patent
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Abstract
Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.
Claims18
A circuit comprising:
- a bit line comprising a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to cause a voltage drop between the first section and the second section, wherein the first section is coupled to a read circuit for a memory;
- and
- a keeper circuit comprising a driver circuit, the driver circuit comprising a first transistor and a second transistor, wherein the first section is connected to a first gate of the first transistor;
- and wherein the second section is connected to a second gate of the second transistor;
- wherein the keeper circuit further comprises a keeper inverter having a third transistor, a fourth transistor, and a fifth transistor;
- wherein an output of the driver circuit is coupled to a third gate of the third transistor and a fourth gate of the fourth transistor;
- wherein a drain of the fourth transistor is coupled to the first section;
- and
- wherein the first transistor is connected to a first power supply and the second transistor is connected to a second power supply.
A memory comprising:
- at least one memory block comprising a plurality of memory cells coupled to a pair of bit lines;
- a global bit line coupled to the at least one memory block, the global bit line comprises a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to cause a voltage drop between the first section and the second section;
- a keeper circuit comprising a driver circuit, the driver circuit comprising a first transistor and a second transistor, wherein the first section is connected to a first gate of the first transistor;
- and wherein the second section is connected to a second gate of the second transistor;
- wherein the keeper circuit further comprises a keeper inverter having a third transistor, a fourth transistor, and a fifth transistor;
- wherein an output of the driver circuit is coupled to a third gate of the third transistor and a fourth gate of the fourth transistor;
- wherein a drain of the fourth transistor is coupled to the first section;
- and
- wherein the first transistor is connected to a first power supply and the second transistor is connected to a second power supply.
Dependencies are inferred from the claim text.