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US 10,832,761 B2Granted
Polarization gate stack SRAM
AssigneeIntel Corporation
InventorsDaniel H. Morris, Uygar E. Avci, Ian A. Young
Life of this patent
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Abstract
One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.
Claims20
An SRAM memory cell, comprising:
- a first invertor having a first pull up transistor and a first pull down transistor, wherein the first pull down transistor comprises a first gate stack having a ferroelectric material between a gate oxide and a channel of the first pull down transistor, the ferroelectric material in contact with the gate oxide;
- a first access transistor coupled to the first invertor, wherein the first access transistor comprises a second gate stack having a ferroelectric material;
- a second invertor having a second pull up transistor and a second pull down transistor;
- and
- a second access transistor coupled to the second invertor.
2 more elements
An SRAM memory cell, comprising:
- a first invertor having a first pull up transistor and a first pull down transistor, wherein the first pull down transistor comprises a first gate stack having a polarization layer between a gate oxide and a channel of the first pull down transistor, the polarization layer in contact with the gate oxide;
- a first access transistor coupled to the first invertor, wherein the first access transistor comprises a second gate stack having a polarization layer;
- a second invertor having a second pull up transistor and a second pull down transistor;
- and
- a second access transistor coupled to the second invertor.
2 more elements
A system, comprising:
- a processor;
- and
- a memory array coupled to the processor, the memory array comprising an SRAM memory cell, and the SRAM memory cell comprising:
- a first invertor having a first pull up transistor and a first pull down transistor, wherein the first pull down transistor comprises a first gate stack having a ferroelectric material between a gate oxide and a channel of the first pull down transistor, the ferroelectric material in contact with the gate oxide;
- a first access transistor coupled to the first invertor, wherein the first access transistor comprises a second gate stack having a ferroelectric material;
- a second invertor having a second pull up transistor and a second pull down transistor;
- and
- a second access transistor coupled to the second invertor.
5 more elements
Dependencies are inferred from the claim text.