Systems and methods for improving write preambles in DDR memory devices
AssigneeMicron Technology, P.C.
InventorsDaniel B. Penney, David R. Brown, Gary L. Howe
Life of this patent
Estimating the term…
Abstract
A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.
Claims20
A memory device, comprising:
- data write circuitry configured to:
- capture a first write command received via an external input/output (I/O) interface;
- generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command;
- and
- write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart comprises a command to start a memory write that is generated internally in the memory device.
A method, comprising:
- capturing a first write command via a memory device;
- generating, via the memory device, a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command;
- and
- writing, via the memory device, a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart comprises a command to start a memory write that is generated internally in the memory device.
A memory device, comprising:
- a memory bank configured to store data;
- an input/output (I/O) interface configured to receive a first write command;
- a write command-to-write command counter system configured to generate a partial write preamble signal (PartialWPre) based on a clock (CLK) waveform and the first write command;
- and
- a data strobe cycle counter configured to generate a first internal write start (InternalWrStart) based on a data strobe waveform and the PartialWPre, wherein the memory device is configured to use the PartialWPre to generate the first InternalWrStart internally and in a data strobe (DQS) domain and to write a first one or more data bits into the memory bank based on the first write start.
Dependencies are inferred from the claim text.