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US 10,832,759 B2Granted
Half-width, double pumped data path
AssigneeMicron Technology, Inc.
InventorMark K. Hadrick
Life of this patent
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Abstract
Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.
Claims17
A memory device, comprising:
- a memory bank comprising memory cells, wherein each of the memory cells comprises a respective stored word having a first data width;
- a data path comprising a data bus, wherein the data bus has a second data width that is smaller than the first data width;
- splitting circuitry configured to split a stored word into a plurality of short words, each short word having the second data width;
- a first data bus driver configured to receive a first short word of the plurality of short words;
- and
- a second data bus driver configured to receive a second short word of the plurality of short words.
3 more elements
A method of operation for a delay element of a memory device comprising:
- receiving a strobe signal comprising a first pulse and a second pulse;
- providing, to first interface circuitry coupled to a first data path, a first activation signal based on the first pulse, wherein the first data path and the first interface circuitry comprise a first data width;
- providing, to a second interface circuitry coupled to the first data path, a second activation signal based on the second pulse;
- providing, to a memory bank, a bank activation signal based on the first pulse;
- splitting the first data path to a second data path and a third data path, wherein the second and data path is a second data width and the third data path is a third width, and wherein the second and third data widths are half of the first data width;
- and
- providing, to the memory bank, the bank activation signal based on the second pulse from the second interface circuitry, wherein the second interface circuitry is coupled to the second or third data path.
4 more elements
A memory device, comprising:
- a first data bus configured to have a first data width;
- a memory array coupled to the first data bus;
- a second data bus configured to have a second data width that is smaller than the first data width;
- control logic configured to:
- receive a strobe signal comprising a first pulse and a second pulse;
- provide a first timing signal in response to the first pulse;
- and
- provide a second timing signal in response to second pulse.
5 more elements
Dependencies are inferred from the claim text.