Receiver for and method of implementing a receiver in an integrated circuit device
AssigneeXilinx, Inc.
InventorsPaolo Novellini, Giovanni Guasti
Life of this patent
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Abstract
A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.
Claims20
A receiver implemented in an integrated circuit device, the receiver comprising:
- a first receiver circuit configured to receive first data at a first receiver input, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal;
- and
- a latency mirror circuit configured to receive second data at a second receiver input, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal;
- and
- a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.
A method of receiving data in an integrated circuit device, the method comprising:
- receiving first data at a first receiver input of a first receiver circuit, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal;
- and
- receiving second data at a second receiver input of a latency mirror circuit, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal;
- detecting a latency in the second data;
- and
- adjusting a phase of the first clock signal used to receive the first data in the first receiver circuit.
Dependencies are inferred from the claim text.