Negative voltage generation for computer memory

A system comprising a circuit configured to:

• enable a first negative word line voltage (VWL) clock generator;
• provide, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump, wherein the first pump clock signal is out of phase with the second pump clock signal;
• generate a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module;
• compare the VWL to a VWL reference voltage;
• and
• based on the VWL being below the VWL reference voltage, disable the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.

A device, comprising logic configured to:

• enable a first negative word line voltage (VWL) clock generator;
• provide, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump, wherein the first pump clock signal is out of phase with the second pump clock signal;
• generate a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module;
• compare the VWL to a VWL reference voltage;
• and
• based on the VWL being below the VWL reference voltage, disable the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.