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US 10,832,752 B2Granted
Memory write and read assistance using negative differential resistance devices
AssigneeThe Regents of the University of California
InventorsPuneet Gupta, Andrew S. Pan, Shaodi Wang
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Abstract
A random access memory (RAM) includes a bit-line, a source-line, a memory cell connected to the bit-line and the source-line, and a read/write circuit connected to the bit-line and the source-line and including a negative differential resistance (NDR) device.
Claims19
A random access memory (RAM) comprising:
- a bit-line;
- a source-line;
- a memory cell connected to the bit-line and the source-line;
- and
- a read/write circuit connected to the bit-line and the source-line and including a negative differential resistance (NDR) device.
2 more elements
A method of programming a multi-level-cell memory, comprising:
- providing a plurality of NDR devices having different, respective NDR characteristics;
- selectively connecting a first one of the NDR devices in series with a multi-level cell;
- and
- generating a write current through the multi-level cell and the first one of the NDR devices.
1 more element
A method of programming a multi-level-cell memory, comprising:
- providing a NDR device connected in series with a multi-level cell, the NDR device being tunable according to a control bias;
- applying the control bias to the NDR device to specify a first NDR characteristic of the NDR device;
- and
- generating a write current through the multi-level cell and the NDR device having the first NDR characteristic to program the multi-level cell to a first state.
1 more element
Dependencies are inferred from the claim text.