Clocked commands timing adjustments method in synchronous semiconductor integrated circuits

A method in a microprocessor integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in a macro block of the microprocessor integrated circuit, the method comprising:

• receiving the command signal for accessing the memory element in the macro block of the microprocessor integrated circuit, the memory element comprising one of a memory array, a register, or a bank of registers, wherein the command signal is a read command signal for reading data from the memory element in the macro block of the microprocessor integrated circuit, or a write command signal for writing data to the memory element in the macro block of the microprocessor integrated circuit;
• detecting the input clock signal having a clock frequency above or below a frequency threshold, wherein the detecting comprises low pass filtering the input clock signal at the frequency threshold;
• generating a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold;
• generating the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold;
• adjusting the command signal by a first timing latency to generate a timing adjusted control signal, the first timing latency being one or more clock periods of the input clock signal;
• adjusting the first timing latency in response to the clock detect output signal;
• applying the timing adjusted control signal to the memory element to access the memory element to obtain read data from the memory element in response to the command signal being the read command signal, the memory element providing the read data under the control of the timing adjusted control signal;
• and
• applying the timing adjusted control signal to the memory element to access the memory element to provide write data to the memory element in response to the command signal being the write command signal, the memory element capturing the write data under the control of the timing adjusted control signal.