Semiconductor storage device having a driver that applies voltage to memory cells based on location of memory cells and method for controlling the same

A semiconductor storage device comprising:

• a plurality of first wiring lines extending in a first direction and arranged along a second direction that crosses the first direction so as to be parallel to each other;
• a plurality of second wiring lines extending in the second direction and arranged along the first direction so as to be parallel to each other;
• a plurality of memory cells provided at intersections of and between the plurality of first wiring lines and the plurality of second wiring lines;
• a selection unit configured to concurrently select, as selected memory cells, at least two memory cells of a plurality of memory cells that are each between one of the first wiring lines and one of the second wiring lines and are divided into a plurality of sections that are contiguous along the first wiring line, the sections including first and second sections;
• and
• a driver that applies a voltage to selected memory cells through the first wiring lines and the second wiring lines, wherein
• said at least two memory cells are located in the same section and the driver applies a first voltage when the selected memory cells are in the first section and a second voltage, different from the first voltage, when the selected memory cells are in the second section.

A method for controlling a semiconductor storage device including a plurality of first wiring lines extending in a first direction and arranged along a second direction that crosses the first direction so as to be parallel to each other, a plurality of second wiring lines extending in a third direction that crosses the first and second directions and arranged along the second direction so as to be parallel to each other, and a plurality of memory cells provided at intersections of the plurality of first wiring lines and the plurality of second wiring lines, the method comprising:

• concurrently selecting, as selected memory cells, at least two memory cells from a plurality of memory cells that are each between one of the first wiring lines and one of the second wiring lines and are divided into a plurality of sections that are contiguous along the first wiring line, the sections including first and second sections;
• and
• applying a first voltage when the selected memory cells are in the first section and a second voltage, different from the first voltage, when the selected memory cells are in the second section, wherein
• said at least two memory cells are located in the same section.