Gate on-state voltage supply unit, gate on-state voltage supply method, display driving module and display device

A gate on-state voltage supply unit for use in a display device comprising a display driving module, the gate on-state voltage supply unit comprising a shutdown determination module and a voltage supply module, wherein the shutdown determination module is configured to determine whether the display device has been shut down, and when the display device has been shut down, transmit a boosting control signal to the voltage supply module;

• the voltage supply module is configured to, upon the receipt of the boosting control signal, boost a gate on-state voltage to acquire a boosted gate on-state voltage, and apply the boosted gate on-state voltage to a gate driving circuit of the display driving module;
• and wherein the shutdown determination module comprises a voltage detection sub-module, a first comparator, a second comparator, a phase inverter and an AND gate;
• the voltage detection sub-module is configured to detect the core voltage at a regular interval;
• a positive phase input end of the first comparator is configured to receive an n.sup.th core voltage detected by the voltage detection sub-module for the n.sup.th time, a negative phase input end of the first comparator is configured to receive a threshold core voltage, and an output end of the first comparator is connected to a first input end of the AND gate;
• the first comparator is configured to output a high level signal when the n.sup.th core voltage is greater than the threshold core voltage, and output a low level signal when the n.sup.th core voltage is smaller than the threshold core voltage, where n is a positive integer;
• a positive phase input end of the second comparator is configured to receive an (n+1).sup.th core voltage detected by the voltage detection sub-module for the (n+1).sup.th time, a negative phase input end of the second comparator is configured to receive the threshold core voltage, and an output end of the second comparator is connected to an input end of the phase inverter;
• the second comparator is configured to output a high level signal when the (n+.sup.1).sup.th core voltage is greater than the threshold core voltage, and output a low level signal when the (n+1).sup.th core voltage is smaller than the threshold core voltage;
• an output end of the phase inverter is connected to a second input end of the AND gate;
• the phase inverter is configured to output a low level signal when the input end of the phase inverter has received a high level signal, and output a high level signal when the input end of the phase inverter has received a low level signal;
• and the AND gate is configured to output the boosting control signal via the output end of the AND gate when the first input end and the second input end of the AND gate have received a high level signal, and output a maintenance control signal via the output end of the AND gate when the first input end and/or the second input end of the AND gate have received a low level signal.