Digital-drive pulse-width-modulated output system

A method of controlling an active-matrix digital PWM display, comprising:

• providing an active-matrix digital PWM display having a display area, wherein the PWM display comprises
• an array of pixels forming rows and columns disposed in the display area, each pixel comprising two or more output devices that are each operable to output a different color of light, a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital pixel value during an uninterrupted load time period, and a drive circuit responsive to a pulse-width-modulation (PWM) timing signal and to the multi-bit digital pixel value to drive the two or more output devices during an uninterrupted output time period subsequent to the load time period,
• an array of row-select lines, each row-select line connected in common to a different row of pixels,
• an array of column-data lines connected in common to each column of pixels, and
• an array of row controllers each serially connected to another of the row controllers, the row controllers having separate, independent and distinct substrates external to the array of pixels, each row controller connected to each pixel in a row of pixels and providing in common to each pixel in the row the load timing signal during the load time period and the PWM timing signal during the output time period, wherein
• the PWM timing signal has multiple different PWM time periods that are sequentially provided at different times to the pixels, each timing period having a different temporal length corresponding to a different bit of the multi-bit digital pixel value, wherein each row controller provides an output time period for each output device that is greater than or equal to twice the entire duration of the PWM timing signal for all of the bits combined in each entire multi-bit digital pixel value;
• providing an array of multi-bit digital pixel values having rows and columns of multi-bit digital pixel values corresponding to the rows and columns of pixels in the array of pixels;
• providing a load signal on the row-select line of a row of pixels with the row controller connected to the row-select line and, at the same time, sequentially providing the bits of the corresponding multi-bit digital pixel values to the column-data lines during a load time period;
• and
• subsequent to the load time period, providing a PWM timing signal one or more times to the row-select line during the output time period.