Pixel circuit, method for driving method, display panel, and display device

A pixel circuit, comprising:

• a scan control circuit, a latch circuit, a charging control circuit, and a pixel electrode, wherein:
• the scan control circuit is configured to output a data signal to a first node in response to a gate scan signal;
• the latch circuit is configured to latch signals of the first node and a second node response to a signal of the first node;
• and
• the charging control circuit is configured to output a first display voltage signal to the pixel electrode in response to the signal of the first node and a charging control signal, and to output a second display voltage signal to the pixel electrode in response to the signal of the second node and the charging control signal;
• wherein the latch circuit comprises:
• a first sub-latch circuit and a second sub-latch circuit, wherein:
• the first sub-latch circuit is configured to latch the signal of the second node as a second reference voltage signal or a first reference voltage signal in response to the signal of the first node;
• and
• the second sub-latch circuit is configured to latch the signal of the first node as the first reference voltage signal or the second reference voltage signal in response to the signal of the second node;
• wherein the first sub-latch circuit comprises:
• a first switch transistor, a second switch transistor, a third switch transistor, and a fourth switch transistor, wherein:
• the first switch transistor has a gate coupled with the first node, a first electrode configured to receive the second reference voltage signal, and a second electrode coupled respectively with a second electrode of the second switch transistor and a gate of the third switch transistor;
• the second switch transistor has a gate and a first electrode, both of which are configured to receive the first reference voltage signal;
• the third switch transistor has a first electrode configured to receive the first reference voltage signal, and a second electrode coupled with the second node;
• and
• the fourth switch transistor has a gate coupled with the first node, a first electrode configured to receive the second reference voltage signal, and a second electrode coupled with the second node;
• the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor are of same transistor type.