Display control device, display, and self-test interrupt method

A display, comprising:

• a display panel, and
• a device, the device including:
• a first driving circuit adapted to drive the display panel from a first side and including a first driving circuit input terminal and a first driving circuit multi-stage output terminal;
• a second driving circuit adapted to drive the display panel from a second side and including a second driving circuit input terminal and a second driving circuit multi-stage output terminal;
• and
• a self-test interrupt module having a first self-test interrupt circuit, a second self-test interrupt circuit, first, second, third, fourth, fifth, and sixth transistors, and a first capacitor,
• wherein a first self-test interrupt circuit input terminal is connected to a first driving circuit rear stage output terminal, and a first self-test interrupt circuit output terminal is connected to the first driving circuit,
• wherein a second self-test interrupt circuit input terminal is connected to a second driving circuit rear stage output terminal, and a second self-test interrupt circuit output terminal is connected to the second driving circuit input terminal,
• wherein a start signal terminal of the self-test interrupt module is configured to access a vertical synchronization signal,
• wherein a control electrode of the second transistor is adapted to access a data enable signal, a second electrode of the second transistor is adapted to connect to the common electrode and to a control electrode of the fourth transistor,
• wherein a first electrode of the third transistor is adapted to connect to the positive power input terminal, a control electrode of the third transistor is connected to the first driving circuit output terminal, a second electrode of the third transistor is respectively connected to a first electrode of the fourth transistor, a control electrode of the fifth transistor, and a first electrode of the sixth transistor,
• wherein a second electrode of the fourth transistor is adapted to connect to the negative power input terminal,
• wherein a first electrode of the fifth transistor is adapted to access the vertical synchronization signal, and a second electrode of the fifth transistor is connected to the first driving circuit input terminal,
• wherein a control electrode of the sixth transistor is adapted to access a scan signal, and the scan signal is adapted to perform line scan on the display panel,
• wherein a second electrode of the sixth transistor is configured to be connected to the negative power input terminal, a first end of the first capacitor is connected to the control electrode of the fifth transistor, and a second end of the first capacitor is connected to the second electrode of the fifth transistor, and
• wherein the self-test interrupt module is adapted to disconnect an input path of the vertical synchronization signal to the first driving circuit when a first signal fed back by the first driving circuit is abnormal, or disconnect the input path of the vertical synchronization signal to the second driving circuit when a second signal fed back by the second driving circuit is abnormal.

A self-test interrupt method of a device, the device comprising a first driving circuit having a first driving circuit input terminal and a first driving circuit multi-stage output terminal and adapted to drive a display panel from a first side, wherein the display panel comprises a positive power input terminal adapted to connect to a gate-on power supply, a negative power input terminal adapted to connect to a gate-off power supply, and a common electrode adapted to access a common voltage, a second driving circuit having a second driving circuit input terminal and a second driving circuit multi-stage output terminal and adapted to drive the display panel from a second side, and a self-test interrupt module including a first self-test interrupt circuit and a second self-test interrupt circuit, wherein the first self-test interrupt circuit includes first, second, third, fourth, fifth, and sixth transistors, and a first capacitor, and wherein a first electrode of the first transistor is adapted to connect to the positive power input terminal, a control electrode of the first transistor is adapted to connect to the first driving circuit output terminal, and a second electrode of the first transistor is adapted to connect to a first electrode of the second transistor;

• wherein a first self-test interrupt circuit input terminal is connected to a first driving circuit rear stage output terminal, and a first self-test interrupt circuit output terminal is connected to the first driving circuit input terminal, wherein a second self-test interrupt circuit input terminal is connected to a second driving circuit rear stage output terminal, and a second self-test interrupt circuit output terminal is connected to the second driving circuit input terminal, wherein a start signal terminal of the self-test interrupt module is configured to access a vertical synchronization signal wherein a control electrode of the second transistor is adapted to access a data enable signal, a second electrode of the second transistor is adapted to connect to the common electrode and to a control electrode of the fourth transistor, wherein a first electrode of the third transistor is adapted to connect to the positive power input terminal, a control electrode of the third transistor is connected to the first driving circuit output terminal, a second electrode of the third transistor is respectively connected to a first electrode of the fourth transistor, a control electrode of the fifth transistor, and a first electrode of the sixth transistor, wherein a second electrode of the fourth transistor is adapted to connect to the negative power input terminal, wherein a first electrode of the fifth transistor is adapted to access the vertical synchronization signal, and a second electrode of the fifth transistor is connected to the first driving circuit input terminal, wherein a control electrode of the sixth transistor is adapted to access a scan signal, and the scan signal is adapted to perform line scan on the display panel, wherein a second electrode of the sixth transistor is configured to be connected to the negative power input terminal, a first end of the first capacitor is connected to the control electrode of the fifth transistor, and a second end of the first capacitor is connected to the second electrode of the fifth transistor,
• the self-test interrupt method comprising:
• acquiring a first signal fed back by the first driving circuit and a second signal fed back by the second driving circuit;
• and
• disconnecting an input path of the vertical synchronization signal to the first driving circuit when the first signal is abnormal, disconnecting the input path of the vertical synchronization signal to the second driving circuit when the second signal is abnormal.