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US 10,832,127 B2Granted
Three-dimensional integration of neurosynaptic chips
AssigneeSamsung Electronics Co., Ltd.
InventorsQing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
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Abstract
A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.
Claims20
A method comprising:
- forming one or more neuron layers comprising a plurality of computing elements;
- forming on top of one of the one or more neuron layers a plurality of synapse layers stacked thereon each layer comprising an array of memory elements, wherein the array comprises a plurality of rows and a plurality of columns;
- and
- forming a plurality of staggered through-silicon vias (TSVs), wherein each of the staggered TSVs connects the one neuron layer to a respective one of the plurality of synapse layers, wherein each of the staggered TSVs are configured to be orthogonal to the one neuron layer, wherein a first set of the plurality of TSVs are horizontally offset from a second set of the plurality of TSVs and a third set of the plurality of TSVs, wherein a portion of the horizontally offset TSVs each have staggering vertical heights, and further wherein a portion of each of the first set of the plurality of TSVs, the second set of the plurality of TSVs and the third set of the plurality of TSVs are connected to each row of the array of the respective synapse layer in a left-right staggered manner and another portion of each of the first set of the plurality of TSVs, the second set of the plurality of TSVs and the third set of the plurality of TSVs are connected to each column of the array of the respective synapse layer in a down-up staggered manner;
- wherein the plurality of staggered TSVs operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the plurality of synapse layers.
2 more elements
An apparatus, comprising:
- one or more neuron layers each comprising a plurality of computing elements;
- a plurality of synapse layers stacked on top of one of the one or more neuron layers wherein each of the plurality of synapse layers comprises an array of memory elements, wherein the array comprises a plurality of rows and a plurality of columns;
- and
- a plurality of staggered through-silicon vias (TSVs) each connecting the one neuron layer to a respective one of the plurality of synapse layers, wherein each of the staggered TSVs are configured to be orthogonal to the one neuron layer, wherein a first set of the plurality of TSVs are horizontally offset from a second set of the plurality of TSVs and a third set of the plurality of TSVs, wherein a portion of the horizontally offset TSVs each have staggering vertical heights, and further wherein a portion of each of the first set of the plurality of TSVs, the second set of the plurality of TSVs and the third set of the plurality of TSVs are connected to each row of the array of the respective synapse layer in a left-right staggered manner and another portion of each of the first set of the plurality of TSVs, the second set of the plurality of TSVs and the third set of the plurality of TSVs are connected to each column of the array of the respective synapse layer in a down-up staggered manner;
- wherein the plurality of staggered TSVs operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the plurality of synapse layers.
2 more elements
A method comprising:
- forming a synapse chip core layer;
- forming on top of the synapse chip core layer a plurality of paralleled synapse circuit layers wherein each of the a plurality of paralleled synapse circuit layers comprises an array of synapse circuits, wherein the array comprises a plurality of rows and a plurality of columns;
- and
- forming a plurality of staggered through-silicon vias (TSVs) connecting each of the paralleled synapse circuit layers to the synapse chip core layer, wherein a first set of the plurality of TSVs are horizontally offset from a second set of the plurality of TSVs and a third set of the plurality of TSVs, wherein a portion of the horizontally offset TSVs each have staggering vertical heights, and further wherein a portion of each of the first set of the plurality of TSVs, the second set of the plurality of TSVs and the third set of the plurality of TSVs are connected to each row of the array of a respective paralleled synapse circuit layers in a left-right staggered manner and another portion of each of the first set of the plurality of TSVs, the second set of the plurality of TSVs and the third set of the plurality of TSVs are connected to each column of the array of the respective paralleled synapse circuit layers in a down-up staggered manner;
- wherein the plurality of staggered TSVs operate as communication links between the synapse chip core layer and each of the one or more paralleled synapse circuit layers.
2 more elements
Dependencies are inferred from the claim text.