US 10,826,525 B1 · Nonlinear data conversion for multi-quadrant multiplication in artificial intelligence

Abstract

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Claims13

Dependent claims

A non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method comprising:

generating a non-linear Most-Significant-Portion (MSP) analog output signal (SoMSPN) that is proportional to a MSP reference signal (SrMSP), and is responsive to a bank of Most-Significant-Bits (MSBs) of a digital input word (DiMSP);
generating a linear Least-Significant-Portion (LSP) analog output signal (SoLSPL) that is proportional to a LSP reference signal (SrLSP), and is responsive to a bank of Least-Significant-Bits (LSBs) of a digital word (DiLSP), and is responsive to the DiMSP word;
combining the SoMPSN signal and the SoLSPL signal to generate a non-linear analog output signal (SoN) that is proportional to a reference signal (SR), and is responsive to a digital word (DI),
wherein the SoLSPL signal is a straight-line approximation between non-linear segments of the (SoMSPN) signal;
wherein the SrMSP signal, and the SrLSP signal, are each proportional to the SR signal;
and
wherein the DI word is comprised of the DiMSP word and the DiLSP word;
generating the SoLSPL signal by a plurality of linear LSP Digital-to-Analog Converters (DACLSPL)s comprised of a first linear LSP DAC (DAC1LSPL), and a second linear LSP DAC (DAC2LSPL);
generating an output signal (So1LSPL) by the DAC1LSPL that is proportional to a first LSP reference signal (Sr1LSP), and is responsive to the DiMSP word;
combining the So1LSPL signal with a reference offset signal (SrOFS) to generate a second reference signal (Sr2LSPL);
receiving the Sr2LSPL signal into a reference input port (Ar2LSPL) of the DAC2LSPL;
and
generating the SoLSPL signal at an output port (Ao2LSPL) of the DAC2LSPL that is responsive to the DiLSP word and the DiMSP word.

10 more elements

A non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method comprising:

generating a non-linear Most-Significant-Portion (MSP) analog output signal (SoMSPN) that is proportional to a MSP reference signal (SrMSP), and is responsive to a bank of Most-Significant-Bits (MSBs) of a digital input word (DiMSP);
generating a linear Least-Significant-Portion (LSP) analog output signal (SoLSPL) that is proportional to a LSP reference signal (SrLSP), and is responsive to a bank of Least-Significant-Bits (LSBs) of a digital word (DiLSP), and is responsive to the DiMSP word;
combining the SoMPSN signal and the SoLSPL signal to generate a non-linear analog output signal (SoN) that is proportional to a reference signal (SR), and is responsive to a digital word (DI),
wherein the SoLSPL signal is a straight-line approximation between non-linear segments of the (SoMSPN) signal;
wherein the SrMSP signal, and the SrLSP signal, are each proportional to the SR signal;
and wherein the DI word is comprised of the DiMSP word and the DiLSP word;
generating at least one (SoMSPN) by at least one non-linear MSP Digital-to-Analog Converter (DACMSPN);
generating at least one SoLSPL by at least one linear LSP Digital-to-Analog Converter (DACLSPL);
generating at least one SoN signal that is proportional to the reference signal (SR), wherein the at least one SoN signal is responsive to at least one Di word;
wherein the reference network of each of the DACMSPN is comprised of a sequence of non-linearly scaled MSP reference signals (SrMSPN) that are proportional to the SrMSP signal;
wherein the reference network of each of the DACLSPL is comprised of a sequence of scaled LSP reference signals (SrLSPL) that are proportional to the SrLSP signal;
wherein each of the sequence of SrMSPN signals is at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted;
wherein each of the sequence of SrLSPL signals is at least one of binary weighted, linearly weighted, and individually weighted;
and
wherein each of the sequence of SrMSPN signals and each of the sequence of SrLSPL signals are biased from a common reference bias network (RBN).

12 more elements

A non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system comprising:

a first non-linear Digital-to-Analog-Converter (DACQM), the DACQM comprised of a digital input port (DQM), an analog output port (AoQM), and an analog reference input port (ArQM);
a first linear Digital-to-Analog-Converter (DAC1L), the DAC1L comprised of a digital input port (D1L), an analog output port (Ao1L), and an analog reference input port (Ar1L);
a second linear Digital-to-Analog-Converter (DAC2L), the DAC2L comprised of a digital input port (D2L), an analog output port (Ao2L), and an analog reference input port (Ar2L);
a digital input word (D) comprised of a Most-Significant-Bits (MSB)s bank word (DMSP), and a Least-Significant-Bits (LSB)s bank word (DLSP);
a digital multiplier (XML), the XML comprised of an M input digital word port (M), an N input digital word port (N), and an output digital word port (M×N);
the M port for receiving the DMSP bank word;
the N port for receiving the DLSP bank word;
the D1L port coupled to the output digital word port M×N;
the D2L port coupled to the digital word N port;
the DQM port coupled to the digital word M port;
wherein the ArQM port for receiving a first reference signal (SrQM);
wherein the Ar1L port for receiving a second reference signal (Sr1L);
wherein the Ar2L port for receiving a third reference signal (Sr2L);
wherein a sum of signals at the Ao1L and Ao2L ports is a straight-line approximation between non-linear segments of a signal at the AoQM port;
wherein a sum of signals at the AoQM, Ao1L, and Ao2L ports generates a non-linear analog output signal (SoN) at an analog output port AoN;
wherein an analog reference signal (SR) is proportionally scaled to the SrQM, the Sr1L, and the Sr2L signals;
wherein a sequence of non-linear reference signals (SrMSPN), which form a transfer function of the DACQM, are proportional to the SR signal;
wherein the sequence of SrMSPN signals are at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted;
wherein a sequence of linear reference signals (SrLSPL), which form a transfer function of the DAC1L and DAC2L, are proportional to the SR signal;
wherein the sequence of SrLSPL signals are at least one of binary weighted, linearly weighted, and individually weighted;
and
wherein the SoN signal substantially follows one of a square, logarithmic, and non-linear profile, is proportional to the SR signal, and responsive to the D word.

19 more elements

A non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system comprising:

a first non-linear digital-to-analog-converter (DACQM), the DACQM comprised of a digital input port (DQM), an analog output port (AoQM), and an analog reference input port (ArQM);
a first linear digital-to-analog-converter (DAC1L), the DAC1L comprised of a digital input port (D1L), an analog output port (Ao1L), and an analog reference input port (Ar1L);
a second linear digital-to-analog-converter (DAC2L), the DAC2L comprised of a digital input port (D2L), an analog output port (Ao2L), and an analog reference input port (Ar2L);
a digital input word (D) comprised of a Most-Significant-Bits (MSB)s bank word (DMSP) and a Least-Significant-Bits (LSB)s bank word (DLSP);
an MSB bank port (M) for receiving the DMSP word;
an LSB bank port (N) for receiving the DLSP word;
the D1L port coupled to the M port;
the D2L port coupled to the N port;
the DQM port coupled to the M port;
wherein the ArQM port for receiving a first reference signal (SrQM);
wherein the Ar1L port for receiving a second reference signal (Sr1L);
wherein a signal at the Ao1L port (So1L) combined with a third reference offset signal (Sfr2L) for being received by the Ar2L port;
wherein a signal at the Ao1L port is a straight-line approximation between non-linear segments of a signal at the AoQM port;
wherein a sum of signals at the AoQM and the Ao1L ports generates a non-linear analog output signal (SoN) at an analog output port AoN;
wherein an analog reference signal (Sr) is proportionally scaled to the SrQM, the Sr1L, and the Sr2L signals;
wherein a sequence of non-linear reference signals (SrMSPN), which form the transfer function of the DACQM, are proportional to the SR signal;
wherein the sequence of SrMSPN signals are at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted;
wherein the sequence of linear reference signals (SrLSPL), which form the transfer function of the DAC1L are proportional to the SR signal;
wherein the sequence of SrLSPL signals are at least one of binary weighted, linearly weighted, and individually weighted;
and
wherein the SoN signal substantially follows one of a square, logarithmic, and non-linear profile, is proportional to the SR signal, and responsive to the D word.

18 more elements

Dependencies are inferred from the claim text.

Nonlinear data conversion for multi-quadrant multiplication in artificial intelligence

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Nonlinear data conversion for multi-quadrant multiplication in artificial intelligence

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Abstract

Claims13