Analog to digital converter with offset-adjustable comparators

An analog to digital converter with offset adjustable comparators, the analog to digital converter comprising:

• a track and hold circuit, tracking and holding an analog input signal to generate a sampled input signal;
• a clock generator generating clock signals;
• a coarse analog-to-digital conversion (ADC) circuit coupled to the track and hold circuit and comprising L offset-adjustable comparators to generate an L-bit output code, wherein each offset-adjustable comparator has a constant embedded offset as a reference voltage for comparing with the sampled input signal;
• a fine analog-to-digital conversion (ADC) circuit coupled to the coarse ADC circuit and the track and hold circuit and comprising M offset-adjustable comparators to generate a M-bit output code, wherein each of the offset-adjustable comparator has an adaptive embedded offset as a reference voltage that is determined by the L-bit output code of the coarse ADC circuit for comparing with the sampled input signal, and an appropriate input region that the sampled input signal corresponds to is determined based on the L-bit output code of the coarse ADC circuit;
• and
• an encoder combining the L-bit output code of the coarse ADC circuit and the M-bit output code of the fine ADC circuit to output a N-bit digital signal.