PVT-independent fixed delay circuit

A PVT-independent fixed delay circuit, comprising a current generator and an inverter-based time delay unit,

• the inverter-based time delay unit comprising a plurality of inverter units, wherein each inverter unit comprises at least two NMOS transistors M5, M6 and at least two PMOS transistors M7, M8;
• a power source VDD is first input to a source of the PMOS transistor M8, in a sequence of the PMOS transistor M8, the PMOS transistor M7, the NMOS transistor M6 and then the NMOS transistor M5, with drains and sources of the adjacent same-type transistors strung together, and at last is grounded through the source of the NMOS transistor M5, in which a gate of the PMOS transistor M8 is connected to a lead PBIAS;
• a gate of the PMOS transistor M7 and a gate of the NMOS transistor M6 are connected to each other to act as an input A;
• the drain of the PMOS transistor M7 and the drain of the NMOS transistor M6 are both connected to an output Y;
• a gate of the NMOS transistor M5 is connected to a lead NBIAS;
• and the plurality of inverter units are cascaded by series-connecting the leads PBIAS of the inverter units together, series-connecting the leads NBIAS of the inverter units together, and connecting the output Y of a previous inverter unit to the input A of a next inverter unit;
• and
• the current generator having a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS, wherein the power source VDD is first input to sources of the PMOS transistors M3, M4, gates of the PMOS transistor M3, M4 and a drain of the M4 electrically connected together to act as an output of the lead PBIAS, drains of the PMOS transistors M3, M4 being connected to drains of the NMOS transistors M1, M2, respectively, gates of the NMOS transistors M1, M2 and the drain of the M1 being electrically connected together to act as an output of the lead NBIAS, a source of the NMOS transistor M1 being directly grounded, a source of the NMOS transistor M2 being connected to the resistor RS, and then an opposite end of the resistor RS being grounded;
• wherein, the outputs of the leads PBIAS and NBIAS in the current generator are connected to the lead PBIAS and the lead NBIAS of a first inverter unit in the inverter-based time delay unit, respectively;
• the output Y of a last inverter unit functions as the PVT-independent fixed delay circuit's output;
• and the input A of the first inverter unit functions as the PVT-independent fixed delay circuit's input.