Integrating ramp circuit with reduced ramp settling time

An imaging system, comprising:

• an array of pixels to receive image light and generate an image charge voltage signal in response;
• and
• readout circuitry coupled to the receive the image charge voltage signal from the array of pixels and provide a digital representation of the image charge voltage signal in response, the readout circuitry including a comparator to receive the image charge, compare the image charge voltage signal to a ramp signal from a ramp generator, and provide the digital representation of the image charge voltage signal in response, wherein the ramp generator comprises:
• an integrator amplifier having first and second inputs and an output to generate the ramp signal, wherein the integrator amplifier comprises:
• a first stage having first and second inputs and first and second outputs, wherein the first and second inputs of the first stage are coupled to the first and second inputs of the integrator amplifier;
• a second stage, comprising:
• first and second transistors coupled between a power supply rail and ground, wherein a node between the first and second transistors is coupled to the output of the integrator amplifier, wherein a control terminal of the first transistor is coupled to the first output of the first stage, and wherein a control terminal of the second transistor is coupled to the second output of the first stage, wherein a first current flows from the output of the integrator amplifier through the integrator amplifier to ground during a ramp event in the ramp signal generated from the output of the integrator amplifier;
• and
• trimming circuitry coupled between the power supply rail and the output of the integrator amplifier, wherein the trimming circuitry is coupled to provide a second current to the output of the integrator amplifier in response to trimming inputs, wherein the second current substantially matches the first current.

A method for reducing a delay of a ramp event in a ramp signal of a ramp generator, comprising:

• generating the ramp signal at an output of an op amp having first and second inputs, wherein the op amp is included in the ramp generator;
• coupling an integrator capacitor between the first input and the output of the op amp;
• coupling a current source to the first input of the op amp;
• coupling a reference voltage capacitance to the second input of the op amp;
• sampling a reference voltage onto the reference voltage capacitance with a sampling switch coupled between the reference voltage and the reference voltage capacitance;
• and
• reducing the reference voltage sampled onto the reference voltage capacitance during the ramp event in the ramp signal with a tuning circuit coupled to the second input of the op amp to reduce the delay of the ramp event in the ramp signal.

A method for providing a ramp signal in an imaging system, comprising:

• receiving image light with an array of pixels;
• generating an image charge voltage signal in response to said receiving the image light;
• and
• receiving the image charge voltage signal with readout circuitry coupled to the array of pixels;
• providing a digital representation of the image charge voltage signal in response to said receiving the image charge voltage signal, wherein said providing the digital representation comprises:
• comparing the image charge voltage signal to the ramp signal from a ramp generator with a comparator;
• providing the digital representation of the image charge voltage signal in response to said comparing the image charge voltage signal to the ramp signal;
• generating the ramp signal at an output of an op amp having first and second inputs, wherein the op amp is included in a ramp generator;
• coupling an integrator capacitor between the first input and the output of the op amp;
• coupling a current source to the first input of the op amp;
• coupling a reference voltage capacitance to the second input of the op amp;
• sampling a reference voltage onto the reference voltage capacitance with a sampling switch coupled between the reference voltage and the reference voltage capacitance;
• and
• reducing the reference voltage sampled onto the reference voltage capacitance during the ramp event in the ramp signal with a tuning circuit coupled to the second input of the op amp to reduce a delay of the ramp event in the ramp signal.