Back to results
US 10,825,835 B1Granted
IC including standard cells and SRAM cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). At least one first P-type FinFET includes a silicon germanium (SiGe) channel region. At least one second P-type FinFET includes a Si channel region. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth. The first depth is greater than the second depth.
Claims20
An integrated circuit (IC), comprising:
- a plurality of P-type fin field-effect transistors (FinFETs), comprising:
- at least one first P-type FinFET comprising a silicon germanium (SiGe) channel region;
- and
- at least one second P-type FinFET comprising a Si channel region,
- wherein source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth,
- wherein the first depth is greater than the second depth.
3 more elements
An integrated circuit (IC), comprising:
- a logic array comprising a plurality of logic cells arranged in rows and columns, wherein each of the logic cells comprises at least one first P-type fin field-effect transistor (FinFET) having a silicon germanium (SiGe) channel region;
- and
- a memory array comprising a plurality of memory cells arranged in rows and columns, wherein each of the memory cells comprises at least one second P-type FinFET having a Si channel region,
- wherein the source/drain regions of the first P-type FinFETs and the source/drain regions of the second P-type FinFETs comprise boron-doped SiGe,
- wherein source/drain regions of the second P-type FinFET are shallower than source/drain regions of the first P-type FinFET.
2 more elements
An integrated circuit (IC), comprising:
- a logic array formed by a plurality of logic cells, wherein each of the logic cells comprises a plurality of first P-type fin field-effect transistors (FinFETs);
- and
- a memory array formed by a plurality of memory cells, wherein each of the memory cells comprises a plurality of second P-type FinFETs,
- wherein the first P-type FinFETs of each of the logic cells in the logic array share a discontinuous semiconductor fin comprising silicon germanium (SiGe), and the second P-type FinFETs of the memory cells positioned in the same column of the memory array share a continuous semiconductor fin comprising Si,
- wherein source/drain regions of the second P-type FinFET are shallower than source/drain regions of the first P-type FinFET.
2 more elements
Dependencies are inferred from the claim text.