Concurrent multi-bit adder
AssigneeGSI Technology, Inc.
InventorMoshe Lazer
Life of this patent
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Abstract
A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored in a different column of the array and each add operation occurs in its associated different column.
Claims12
A method for an associative memory device, the method comprising:
- in parallel, performing multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array,
- wherein each pair of said P pairs is stored in a different column of said array and each add operation occurs in its associated different column.
A system comprising:
- a non-destructive associative memory array comprising a plurality of sections, each section comprising cells arranged in rows and columns, to store bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j;
- and
- a concurrent adder to, in parallel, perform multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array,
- wherein each pair of said P pairs is stored in a different column of said array and each add operation occurs in its associated different column.
Dependencies are inferred from the claim text.