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US 10,819,358 B2Granted
Phase-frequency detector with frequency doubling logic
AssigneeNXP B.V.
InventorSebastien Darfeuille
Life of this patent
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Abstract
Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.
Claims19
An apparatus comprising:
- a correction and signal-drive circuit configured and arranged to generate and correct an output signal, in terms of at least one of phase and frequency, relative to a reference signal having complementary differential signal components and in response to a direction indication signal, wherein the output signal has logic states which alternate in response to the reference signal for characterizing the frequency and phase;
- a phase-frequency detection circuit including logic circuitry configured and arranged to respond to the reference signal and to a feedback signal by generating and updating the direction indication signal as a function of each of the logic states of an internal clock signal having risen and having fallen
- a feedback circuit configured and arranged to generate the feedback signal in response to the output signal;
- and
- a signal conversion circuit configured and arranged to generate the complementary differential signal components of the reference signal, wherein the phase-frequency detection circuitry generates and updates the direction indication signal in response to rising or falling edges of each of the differential signal components, and wherein the feedback circuit includes a programmable divider.
2 more elements
An apparatus comprising:
- a correction and signal-drive circuit configured and arranged to generate and correct an output signal, in terms of at least one of phase and frequency, relative to a reference signal having complementary differential signal components and in response to a direction indication signal, wherein the output signal has logic states which alternate in response to the reference signal for characterizing the frequency and phase;
- a phase-frequency detection circuit including logic circuitry configured and arranged to respond to the reference signal and to a feedback signal by generating and updating the direction indication signal as a function of each of the logic states of an internal clock signal having risen and having fallen
- a feedback circuit configured and arranged to generate the feedback signal in response to the output signal, wherein the output signal and reference signal have respective frequencies that relate to each other by a non-integer ratio having a value that depends on the frequency division ratio of a feedback divider in the feedback circuit;
- and the feedback circuit includes a feedback divider circuit configured and arranged with the correction and signal-drive circuit and the phase-frequency detection circuit as part of a fractional-PLL configured to dynamically change the frequency of the feedback signal by updating a division ratio of the feedback divider so that the ratio between the reference signal and the output signal appears as a fixed fractional ratio after integration.
1 more element
An apparatus comprising:
- a correction and signal-drive circuit configured and arranged to generate and correct an output signal, in terms of at least one of phase and frequency, relative to a reference signal having complementary differential signal components and in response to a direction indication signal, wherein the output signal has logic states which alternate in response to the reference signal for characterizing the frequency and phase;
- a phase-frequency detection circuit including logic circuitry configured and arranged to respond to the reference signal and to a feedback signal by generating and updating the direction indication signal as a function of each of the logic states of an internal clock signal having risen and having fallen;
- and
- a feedback circuit configured and arranged to generate the feedback signal in response to the output signal, wherein the output signal and reference signal have respective frequencies that relate to each other by a non-integer ratio having a value that depends on the frequency division ratio of a feedback divider in the feedback circuit;
- and the feedback circuit includes a feedback divider circuit configured and arranged with the correction and signal-drive circuit and the phase-frequency detection circuit as part of a fractional-PLL configured to modulate one or both of the ratio of the feedback divider or an oscillator utilized in generating the output signal.
2 more elements
A method comprising:
- in response to a direction indication signal, correcting an output signal in terms of at least one of phase and frequency relative to a reference signal having complementary differential signal components, wherein the output signal has logic states that alternate in response to the reference signal for characterizing the frequency and phase;
- using logic circuitry configured and arranged as part of a phase-frequency detection circuit to respond to the reference signal and to a feedback signal by generating and updating the direction indication signal as a function of each of the logic states of an internal clock signal having risen and having fallen;
- generating the complementary differential signal components of the reference signal, wherein the phase-frequency detection circuit generates and updates the direction indication signal in response to rising or falling edges of each of the differential signal components;
- and
- coupling, via a feedback circuit, the output signal to provide the feedback signal, wherein the feedback circuit includes a programmable divider.
2 more elements
Dependencies are inferred from the claim text.