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US 10,819,283 B1Granted
Current-mode analog multipliers using substrate bipolar transistors in CMOS for artificial intelligence
OwnerAli Tasdighi Farinventor
Life of this patent
Estimating the term…
Abstract
Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.
Claims10
A multiplication (iMULT) method in an integrated circuit, the iMULT method comprising:
- operating four transistors x-T, r-T, y-T, and z-T, wherein each transistor is a substrate parasitic Bipolar Junction Transistor (T) available in a Complementary Metal Oxide Semiconductor (CMOS), wherein each of a plurality of the Ts has a collector, base, and emitter port, and wherein the T's collector port is a CMOS substrate coupled to a power supply;
- supplying the x-T's emitter port with a x-input current (Ix);
- supplying the r-T's emitter port with a r-input current (Ir);
- supplying the y-T's emitter port with a y-input current (Iy);
- generating a z-output current (Iz) through the z-T's emitter port;
- coupling together a voltage source (V1), and the base ports of the x-T and r-T;
- coupling the base ports of the z-T and y-T together at a first node;
- regulating the first node voltage to substantially equalize the emitter port voltages of the r-T and the y-T;
- and
- regulating the Iz to substantially equalize the emitter port voltages of the x-T and z-T, wherein Iz is substantially equal to Ix×Iy/Ir.
7 more elements
A multiplication (iMULT) method in an integrated circuit, the iMULT method comprising:
- operating four transistors x-T, r-T, y-T, and z-T transistors, wherein each transistor is a substrate parasitic Bipolar Junction Transistor (T) available in a Complementary Metal Oxide Semiconductor (CMOS), wherein each of a plurality of the Ts has a collector, base, and emitter port, and wherein the T's collector port is a CMOS substrate coupled to a power supply;
- supplying the x-T's emitter port with a x-input current (Ix);
- supplying the r-T's emitter port with a r-input current (Ir);
- supplying the y-T's emitter port with a y-input current (Iy);
- generating a z-output current (Iz) through the z-T's emitter port;
- coupling together a voltage source (V1), and the base ports of the y-T and r-T;
- regulating the base port of the x-T to substantially equalize the emitter port voltages of the r-T and x-T;
- regulating the base port voltage of the z-T to substantially equalize the emitter port voltages of the y-T and z-T;
- and
- regulating the Iz to substantially equalize the base port voltages of the x-T and z-T, wherein Iz is substantially equal to Ix×Iy/Ir.
7 more elements
A multiplication (iMULT) method in an integrated circuit, the iMULT method comprising:
- operating four transistors x-T, r-T, y-T, and z-T transistors, wherein each transistor is a substrate parasitic Bipolar Junction Transistor (T) available in a Complementary Metal Oxide Semiconductor (CMOS), wherein each of a plurality of the Ts has a collector, base, and emitter port, and wherein the T's collector port is a CMOS substrate coupled to a power supply;
- supplying the x-T's emitter port with a x-input current (Ix);
- supplying the r-T's emitter port with a r-input current (Ir);
- supplying the y-T's emitter port with a y-input current (Iy);
- generating a z-output current (Iz) through the z-T's emitter port;
- coupling together a voltage source (V1) and the base ports of the x-T, y-T, r-T, and z-T;
- amplifying the voltage difference between the x-T and r-T emitter ports by a factor G to generate a differential output signal (xr);
- amplifying the voltage difference between the z-T and y-T emitter ports by a factor G1 to generate a differential output signal (yz), wherein the factor G1 is substantially equal to the factor G;
- summing the xr and yz differential output signals to generate a combined differential signal;
- and
- regulating the Iz to substantially balance the combined differential signal, wherein Iz is substantially equal to Ix×Iy/Ir.
8 more elements
A multiplication (iMULT) method in an integrated circuit, the iMULT method comprising:
- operating four transistors x-T, r-T, y-T, and z-T transistors, wherein each transistor is a substrate parasitic Bipolar Junction Transistor (T) available in a Complementary Metal Oxide Semiconductor (CMOS), wherein each of a plurality of Ts has a collector, base, and emitter port, and wherein the T's collector port is a CMOS substrate coupled to a power supply;
- supplying the x-T's emitter port with a x-input current (Ix);
- supplying the r-T's emitter port with a r-input current (Ir);
- supplying the y-T's emitter port with a y-input current (Iy);
- generating a z-output current (Iz) through the z-T's emitter port;
- coupling a voltage source (V1) to the base ports x-T, y-T, r-T, and z-T;
- amplifying the voltage difference between the x-T and z-T emitter ports by a factor G to generate an output signal (xz);
- amplifying the voltage difference between the y-T and r-T emitter ports by a factor G1 to generate an output signal (yr), wherein the factor G1 is substantially equal to the factor G;
- and
- regulating the Iz is to substantially balance the xz-gained signal to the yr-gained signal, wherein Iz is substantially equal to Ix×Iy/Ir.
7 more elements
Dependencies are inferred from the claim text.