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US 10,819,278 B2Granted
Oscillator circuit
AssigneeStichting IMEC Nederland
InventorsPaul Mateman, Cui Zhou
Life of this patent
Estimating the term…
Abstract
A differential Colpitts oscillator circuit is described which has center-tapped inductors which are cross-coupled with gates of second transistors of first and second transistor pairs which can reduce the minimum power supply voltage and the bias voltage for the circuit. In addition, a capacitive ladder can be implemented which also has the potential benefit of increased tuning range.
Claims8
A circuit comprising:
- a first transistor and a second transistor;
- a first inductor connected in a first line between a first gate of the first transistor and a connecting point;
- a third transistor and a fourth transistor;
- a second inductor connected in a second line between a third gate of the third transistor and the connecting point;
- a first variable capacitor connected in a third line between (i) a first junction between the first transistor and the second transistor and (ii) a second junction between the third transistor and the fourth transistor;
- and
- a resistor connected to the second transistor and to the fourth transistor,
- characterized in that a fourth gate of the fourth transistor is connected to a first tap point of the first inductor and a second gate of the second transistor is connected to a second tap point of the second inductor,
- the circuit further comprising a capacitive ladder connected between the third line and the first line and between the third line and the second line, the first variable capacitor forming part of the capacitive ladder,
- wherein the capacitive ladder comprises:
- at least a first capacitor pair connected between the first line and the third line;
- at least a second capacitor pair connected between the second line and the third line;
- and
- a second variable capacitor connected between the first and second capacitor pairs configured for determining tuning range of the circuit.
11 more elements
A circuit comprising:
- a first transistor comprising a first terminal and a second terminal that is a gate terminal;
- a second transistor comprising a third terminal, a fourth terminal, and a fifth terminal that is a gate terminal;
- a third transistor comprising a sixth terminal and a seventh terminal that is a gate terminal;
- a fourth transistor comprising an eighth terminal, a ninth terminal, and a tenth terminal that is a gate terminal;
- a first inductor comprising an eleventh terminal, a twelfth terminal, and a first center tap terminal;
- a second inductor comprising a thirteenth terminal, a fourteenth terminal, and a second center tap terminal;
- and
- a resistor comprising a fifteenth terminal,
- wherein the second terminal and the eleventh terminal form a first node,
- wherein the twelfth terminal and the thirteenth terminal form a second node,
- wherein the fourteenth terminal and the seventh terminal form a third node,
- wherein the first terminal and the third terminal form a fourth node,
- wherein the sixth terminal and the eighth terminal form a fifth node,
- wherein the fourth terminal, the ninth terminal, and the fifteenth terminal form a sixth node,
- wherein the fifth terminal and the second center tap terminal form a seventh node, and
- wherein the tenth terminal and the first center tap terminal form an eighth node.
13 more elements
Dependencies are inferred from the claim text.