US 10,805,123 B2Granted

Crosstalk generation and detection for digital isolators

AssigneeTexas Instruments Incorporated

InventorsAtul Singh, Kumar Anurag Shrivastava

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Abstract

A method of detecting crosstalk for a digital isolator having first and second channels including two die with channels including a transmit side, receive side, with ≥1 die including a capacitive barrier for each channel. A first clock signal at a first frequency in a first pulse pattern and a second clock signal at a second frequency in a second pulse pattern are configured, wherein the pulse patterns have a phase difference. The transmit side of the channels each encode their received clock pulse pattern, then modulate with a carrier frequency to provide a fc1 and a fc2 signal, respectively. The receive side of the channels demodulate received signals during a rising or falling edge of their clock signal to generate a delayed received version of the first and second clock pulse pattern. Missing pulses are identified by comparing the delayed received clock pulse patterns to their clock pulse patterns.

Claims28

Dependent claims

A method of making a digital isolator, comprising:

attaching a first semiconductor die to a die pad, the first die including a modulator, a transmitter and a capacitive barrier for each channel of the transmitter;
attaching a second semiconductor die to the die pad, the second die including a demodulator, a receiver and a capacitive barrier for each channel of the receiver;
coupling each capacitive barrier on the first semiconductor die to a respective capacitive barrier on the second semiconductor die with a bond wire;
configuring a first clock signal at a first frequency (Fi) with a first clock period in a first clock pulse pattern and a second clock signal with a second clock period at a different second frequency (F2) in a second clock pulse pattern, wherein clock pulses in the first clock pulse pattern and the second clock pulse pattern have a phase difference,
the transmitter of a first channel encoding the first clock pulse pattern then modulating with a first carrier frequency to provide a fc1 signal and the transmitter of a second channel encoding the second clock pulse pattern then modulating with a second carrier frequency to provide a fc2 signal;
the receiver of the first channel demodulating the fcl signal received during a rising or a falling edge of the F1 to generate a delayed received version of the first clock pulse pattern and the receiver of the second channel demodulating the fc2 signal received during a rising or a falling edge of the F2 to generate a delayed received version of the second clock pulse pattern, and
identifying for missing pulses by comparing the delayed received version of the first clock pulse pattern to the first clock pulse pattern and the delayed received version of the second clock pulse pattern to the second clock pulse pattern.

4 more elements

Automated test equipment (ATE) for crosstalk testing of a multi-channel digital isolator, the ATE comprising:

pattern generation and detection code stored in firmware in a memory associated with a computer of the ATE, the firmware implementing a method of detecting crosstalk for a digital isolator having a first channel and at least a second channel comprising a first die and at least a second die with each the channel include a transmit side including a modulator and a transmitter and a receive side including a receiver and a demodulator coupled by a bond wire, wherein at least one of the first and the second die include a barrier comprising a high voltage (HV) capacitor for each the first and the second channel, the method comprising:
the ATE configuring a first clock signal at a first frequency (F1) with a first clock period in a first clock pulse pattern and a second clock signal with a second clock period at a different second frequency (F2) in a second clock pulse pattern, wherein the clock pulses in the first clock pulse pattern and the second clock pulse pattern have a phase difference,
wherein the transmitter of the first channel encodes the first clock pulse pattern then modulating with a first carrier frequency to provide a fc1 signal and the transmitter of the second channel encoding the second clock pulse pattern then modulating with a second carrier frequency to provide a fc2 signal;
wherein the receiver of the first channel demodulates the fcl signal received during a rising or a falling edge of the F1 to generate a delayed received version of the first clock pulse pattern and the receiver of the second channel demodulates the fc2 signal received during a rising or a falling edge of the F2 to generate a delayed received version of the second clock pulse pattern, and
the ATE identifying for missing pulses by comparing the delayed received version of the first clock pulse pattern to the first clock pulse pattern and the delayed received version of the second clock pulse pattern to the second clock pulse pattern.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/914,753Filed 7 Mar 2018
Published: US 2019/0278245 A112 Sep 2019
Granted: 13 Oct 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H04L 25/0268
Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling: with modulation and subsequent demodulation
G01R 31/317
Testing of electronic circuits, e.g. by signal tracer: testing of digital circuits
G01R 31/31727
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
H03D 3/00
Demodulation of angle-, frequency- or phase- modulated oscillations