Slow clamp circuit for bipolar junction transistor (BJT) buffers
AssigneeTexas Instruments Incorporated
InventorSudheer Prasad
Life of this patent
Estimating the term…
Abstract
A system includes: 1) a buffer circuit; 2) circuitry coupled to an input of the buffer circuit; 3) a load coupled to an output of the buffer circuit; and 4) a clamp circuit coupled between an input of the buffer circuit and the output of the buffer circuit. The clamp circuit includes: 1) a bipolar junction transistor (BJT); 2) a first resistor with a first end coupled to a base terminal of the BJT and with a second end coupled to a collector terminal of the BJT; and 3) a second resistor with a first end coupled to the collector terminal of the BJT and with a second end coupled to the input of the buffer circuit. The second resistor is between an output of the circuitry and the input of the buffer circuit.
Claims21
A system, comprising:
- a buffer circuit having an input and an output;
- an input amplifier having a first input coupled to an input voltage terminal, a second input coupled to the output of the buffer circuit, and an output coupled to the input of the buffer circuit;
- and
- a clamp circuit having a first terminal coupled to the input of the buffer circuit and a second terminal coupled to the output of the buffer circuit, wherein the clamp circuit includes:
- a clamp bipolar junction transistor (BJT) having a base terminal, a collector terminal and an emitter terminal;
- a first resistor having a first lead coupled to the base terminal of the clamp BJT and a second lead coupled to the collector terminal of the clamp BJT;
- and
- a second resistor having a first lead coupled to the collector terminal of the clamp BJT and a second lead coupled to the input of the buffer circuit and the output of the input amplifier.
A device, comprising:
- an input terminal;
- an output terminal;
- a buffer circuit having an output coupled to the output terminal and having an input;
- an input amplifier having a first input coupled to the output of the buffer circuit, a second input coupled to the input terminal and an output coupled to the input of the buffer circuit;
- a clamp circuit having a first terminal coupled to the input of the buffer circuit and a second terminal coupled to the output of the buffer circuit, wherein the clamp circuit includes:
- a clamp bipolar junction transistor (BJT) having a base terminal, a collector terminal and an emitter terminal;
- a first resistor having a first lead coupled to the base terminal of the clamp BJT and a second lead coupled to the collector terminal of the clamp BJT;
- and
- a second resistor having a first lead coupled to the collector terminal of the clamp BJT and a second lead coupled to the input of the buffer circuit.
An integrated circuit, comprising:
- an input terminal;
- an output terminal;
- a bipolar junction transistor (BJT) buffer circuit having an output coupled to the output terminal and having an input;
- an input amplifier having a first input coupled to the output of the BJT buffer circuit, a second input coupled to the input terminal and an output coupled to the input of the BJT buffer circuit;
- a clamp circuit having a first terminal coupled to the input of the buffer circuit and a second terminal coupled to the output terminal, wherein the clamp circuit is configured to delay clamping for at least a threshold amount of time using a BJT having a base terminal coupled to a first lead of a base resistor, a collector terminal coupled to a second lead of the base resistor, and a collector terminal coupled to the output terminal.
Dependencies are inferred from the claim text.