Instruction memory
AssigneeAmazon Technologies, Inc.
InventorsThomas A. Volpe, Nafea Bshara
Life of this patent
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Abstract
Provided are systems and methods for implementing a memory for an integrated circuit device. In various examples, the integrated circuit can operate the memory as a FIFO, where each address in the FIFO is directly addressable. The integrated circuit can include a first register for storing a head pointer and a second register for storing a tail pointer. When new data is written to the memory, the data cat be written starting at the tail pointer location, without the tail pointer being modified. The tail pointer can be incremented using write transactions received from external to the integrated circuit.
Claims23
An integrated circuit for executing program instructions, comprising:
- a memory, wherein each address in the memory is directly addressable, and wherein each address can be written to by a write transaction that specifies the address;
- a first register operable to store a head pointer referring to a first address in the memory, wherein the first address can store a next instruction to read from the memory;
- a second register operable to store a tail pointer referring to a second address in the memory, wherein the second address can store a last instruction to read from the memory, and wherein the tail pointer indicates an address at which new instructions can be written, and wherein the tail pointer is not modified when new data is written to the memory;
- an execution circuit operable to perform operations on data read from the memory;
- and
- a fetch circuit, operable to:
- determine that the head pointer is referring to a different address than an address referred to by the tail pointer;
- initiate a read of the memory, wherein the read causes data at the address referred to by the head pointer to be provided to the execution circuit to be operated upon;
- increment the head pointer to refer at a third address, wherein the third address is one address after the first address;
- and
- determine, after incrementing the head pointer, whether the head pointer and the tail pointer are referring to a same address, wherein, when the head pointer and the tail pointer are referring to different addresses, the fetch circuit initiates another read of the memory, and wherein, when the head pointer and the tail pointer are referring to the same address, the fetch circuit stops initiating reads of the memory.
An integrated circuit, comprising:
- a memory, wherein the integrated circuit operates the memory as a first-in, first-out buffer, and wherein each address in the memory is directly addressable;
- a first register operable to store a head pointer that refers to a first address in the memory;
- a second register operable to store a tail pointer that refers to a second address in the memory, wherein the tail pointer is not modified when new data is written to the memory;
- a fetch circuit, operable to:
- determine that the first address is different from the second address;
- initiate a read of data at the first address;
- increment the head pointer to point to a next address;
- and
- determine that the next address is a same address as the second address, wherein, based on the head pointer pointing to a same address as the tail pointer, the fetch circuit stops initiating reads of the memory.
A method implemented using an integrated circuit, comprising:
- receiving a write transaction for writing a set of data to a memory of the integrated circuit, wherein the integrated circuit stores a head pointer and a tail pointer, the head pointer and the tail pointer each referring to addresses in the memory, and wherein the memory is directly addressable;
- sequentially writing the set of data to the memory, wherein a first data from the set of data is written to a first address of the memory, wherein the tail pointer is not modified as a result of writing the set of data;
- receiving a transaction for updating the tail pointer, the transaction including a value;
- incrementing the tail pointer by a number of addresses equaling the value, wherein, after being incremented, the tail pointer refers to a second address;
- determining that the head pointer is referring to an address other than the second address;
- initiating a read of data at the address referred to by the head pointer;
- and
- incrementing the head pointer to refer to a next address.
Dependencies are inferred from the claim text.