Method of fabricating novel packages for electronic components

A method of fabricating packaged components, said method comprising the stages of:

• a) Obtaining an active membrane layer on a carrier substrate;
• b) Depositing a front electrode onto a front of the active membrane layer;
• c) Obtaining an inner front section comprising at least a silicon handle or wafer;
• d) Attaching an inner front end section to an outer surface of the front electrode;
• e) Detaching the carrier substrate from a back surface of an active membrane on the opposite surface from the front surface on which the front electrode is deposited;
• f) Optionally trimming the active membrane to a specified thickness;
• g) Patterning the active membrane layer into an array of at least one island of membrane;
• h) Selectively removing the front electrode and bonding layer;
• i) Selectively applying an inner passivation layer;
• j) Selectively depositing a back electrode layer and optionally a frame layer and optionally a mass loading layer on the thus exposed back surface of the active membrane;
• k) Selectively depositing an outer passivation layer patterned to selectively expose a first route and a second route for respectively routing signals from external contacts to the front and back electrodes;
• l) Selectively depositing a first internal conductive route that is coupled to the back electrode layer and a second internal route that is coupled to the front electrode layer by a part of the back electrode layer isolated from the membrane by way of a filled through-via traversing the inner passivation layer;
• m) Optionally thinning the silicon handle or wafer to a desired thickness;
• n) Creating an array of at least one front cavity by selectively removing at least the silicon handle or wafer of the inner front end section, to fabricate a cavity opposite each island of membrane;
• o) Obtaining an outer front end section and bonding the outer front end section to the inner front end section such that the outer front end section spans across and seals the at least one cavity of the array of front cavities;
• p) Optionally thinning the outer front end section;
• q) Optionally trimming the exposed outer passivation layer;
• r) Applying an organic back end comprising a selectively deposited inner organic layer comprising an array of back cavities therethrough, comprising one back cavity and a pair of through via holes per trimmed island of active membrane, wherein the through via holes are opposite internal pads of a routing layer, and are open to the routing layer through the apertures in the outer passivation layer, and further comprising back trenches through the inner organic layer, opposite the region wherein the silicon handle or wafer of a front inner layer is exposed by the patterning of the silicon oxide and inner passivation layer;
• s) Selectively applying an outer back organic layer onto an inner back organic layer comprising through via holes over the through via holes in the inner back organic layer and extensions to the back trenches, thereby creating deep trenches, but spanning and sealing the at least one upper cavity;
• t) Optionally fabricating deep trenches on a front side of the package, wherein said deep trenches on the front side are aligned with the deep trenches on the back side of the package and traverse the front outer layer and any package bonding layer to the silicon handle or wafer of the front inner layer;
• u) Optionally applying a sealing liner coating onto the outer surface of both the back and front ends and into the deep trenches and then removing the sealing liner coating from in and around the via holes;
• v) Filling the array of via holes through the outer and inner organic layers with a metal that contacts a conductive inner pad layer to create filled vias and extending the filled vias to create external pads;
• w) Applying a barrier layer and solder bumps to the external pads of the filled vias;
• x) Reflowing the solder bumps;
• y) Optionally thinning the outer back layer of a front end section;
• and
• z) Dicing arrays into separate component dies.