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US 10,796,751 B1Granted
State change detection for two-terminal memory
AssigneeCrossbar, Inc.
InventorsSang Nguyen, Hagop Nazarian, Tianhong Yan
Life of this patent
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Abstract
A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.
Claims20
A memory device, comprising:
- a plurality of two-terminal memory cells, each coupled to a wordline, wherein a cell of the plurality of two-terminal memory cells comprises a first terminal coupled to the wordline and a second terminal coupled to a bitline;
- and
- a detection circuit that, during application of an electrical stimulus configured to cause a change in state to the cell from a first defined state representing a first binary value to a second defined state representing a second binary value, detects the cell transitioning from the first defined state to the second defined state concurrent with the application of the electrical stimulus, wherein the detection circuit in part comprises:
- a shared node electrically coupled to:
- a cell current line that is connected to the bitline or to the wordline of the cell of the plurality of two-terminal memory cells, wherein a cell current Ic flowing through the cell is configured also to flow to the shared node by way of the cell current line,
- a reference line having a reference current Ir generated by a reference current source that flows to the shared node from the reference line, and
- a detect line that provides a detection current Id that flows to the shared node from a reference voltage on the detect line, and
- a measurement node that has a first value that changes in response to a change in a second value of Id corresponding to the cell transitioning from the first defined state to the second defined state.
5 more elements
A method, comprising:
- transmitting, by a controller of a memory device, an instruction to apply electrical stimuli to a wordline that is coupled to a first terminal of a two-terminal memory cell of the memory device and a bitline that is coupled to a second terminal of the two-terminal memory cell, wherein the electrical stimuli are configured to set the two-terminal memory cell to a first state of a binary value;
- during application of the electrical stimuli, measuring, by a detection circuit of the memory device that comprises no more than three current mirror circuits, an electrical response of the two-terminal memory cell to the electrical stimuli and determining that the two-terminal memory cell is set to the first state;
- transmitting, by the controller, a second instruction to apply a second electrical stimuli to the wordline and to the bitline, wherein the second electrical stimuli are configured to reset the two-terminal memory cell to a second state of the binary value;
- during application of the second electrical stimuli, measuring by the detection circuit a second electrical response of the two-terminal memory cell to the second electrical stimuli and determining that the two-terminal memory cell is reset to the second state;
- and
- in response to the determining the two-terminal memory cell is set to the first state, terminating application of the electrical stimuli.
3 more elements
A memory device, comprising:
- a plurality of two-terminal memory cells, each coupled to a wordline, wherein a cell of the plurality of two-terminal memory cells comprises a first terminal coupled to the wordline and a second terminal coupled to a bitline;
- and
- a detection circuit comprising a reference current source, a first current mirror circuit and a second current mirror circuit that, during application of an electrical stimulus configured to cause a change in state to the cell from a first defined state representing a first binary value to a second defined state representing a second binary value, detects the cell transitioning from the first defined state to the second defined state concurrent with the application of the electrical stimulus, wherein
- the first current mirror circuit comprises:
- a first transistor that shares a common node, by way of an access transistor, with the memory device;
- a first gate line that is coupled to a first gate of the first transistor and a second gate of a second transistor;
- a drain supply line that is coupled to a first drain of the first transistor, to a second drain of the second transistor, and to the reference current source;
- a first source line that is coupled to a first source of the first transistor, coupled to the first gate line and to the first gate and the second gate by way of the first gate line, and coupled to the common node by way of the access transistor;
- and
- a second source line that is coupled to a second source of the second transistor, to a comparison line, and to a third source line of a third transistor that is coupled to the comparison line, wherein the first transistor and the second transistor are part of the first current mirror, and the third transistor is part of the second current mirror.
7 more elements
Dependencies are inferred from the claim text.