US 10,795,853 B2Granted

Multiple dies hardware processors and methods

AssigneeIntel Corporation

InventorsNevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy

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Abstract

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Claims24

Dependent claims

A hardware processor comprising:

a plurality of physically separate dies;
an interconnect to electrically couple the plurality of physically separate dies together;
a first transmitter circuit of a first die of the plurality of physically separate dies;
a second receiver circuit of a second die of the plurality of physically separate dies electrically coupled to the first transmitter circuit of the first die through at least one data lane of the interconnect that corresponds to a clock lane of the interconnect;
and
a clock circuit to receive a request from the first transmitter circuit to change the second receiver circuit to an operating frequency and a clocking rate for the operating frequency, cause a look-up in a data storage device of a predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency from a plurality of predetermined clock phase placements for a first clocking rate for each single frequency of different operating frequencies and for a second, different clocking rate for each single frequency of different operating frequencies, and cause the second receiver circuit to receive data from the first transmitter circuit on the at least one data lane with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency on the clock lane.

3 more elements

A method comprising:

electrically coupling a plurality of physically separate dies together with an interconnect with a first transmitter circuit of a first die of the plurality of physically separate dies electrically coupled to a second receiver circuit of a second die of the plurality of physically separate dies through at least one data lane of the interconnect that corresponds to a clock lane of the interconnect;
receiving a request from the first transmitter circuit to change the second receiver circuit to an operating frequency and a clocking rate for the operating frequency;
performing a look-up in a data storage device of a predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency from a plurality of predetermined clock phase placements for a first clocking rate for each single frequency of different operating frequencies and for a second, different clocking rate for each single frequency of different operating frequencies;
and
receiving data with the second receiver circuit from the first transmitter circuit on the at least one data lane with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency on the clock lane.

2 more elements

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

electrically coupling a plurality of physically separate dies together with an interconnect with a first transmitter circuit of a first die of the plurality of physically separate dies electrically coupled to a second receiver circuit of a second die of the plurality of physically separate dies through at least one data lane of the interconnect that corresponds to a clock lane of the interconnect;
receiving a request from the first transmitter circuit to change the second receiver circuit to an operating frequency and a clocking rate for the operating frequency;
performing a look-up in a data storage device of a predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency from a plurality of predetermined clock phase placements for a first clocking rate for each single frequency of different operating frequencies and for a second, different clocking rate for each single frequency of different operating frequencies;
and
receiving data with the second receiver circuit from the first transmitter circuit on the at least one data lane with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency on the clock lane.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/721,822Filed 30 Sep 2017 · us provisional application
Priority: 10 Oct 2016
Published: US 2018/0101502 A112 Apr 2018
Granted: 6 Oct 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 15/7889
Runtime interface, e.g. data exchange, runtime control: reconfigurable logic implemented as a co-processor
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…