Multi-protocol receiver
AssigneeSynopsys, Inc.
InventorsPrasad Chalasani, Venkata N. S. N. Rao, Majid Jalali Far
Life of this patent
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Abstract
A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.
Claims19
A multi-protocol receiver for receiving one or more input signals comprising:
- a comparator for comparing a reference voltage and a predefined voltage to determine a common mode voltage;
- a protection controller coupled to the comparator, the protection controller configured to generate one or more selection signals based on an output of the comparator;
- a first current mode logic (CML) buffer comprising:
- one or more inputs for receiving the one or more input signals, and
- one or more control inputs for receiving at least a subset of selection signals from the protection controller;
- and
- a second CML buffer coupled to the first CML, the second CML comprising:
- a first set of inputs for receiving the one or more input signals,
- a second set of inputs for receiving one or more output signals from the first CML buffer, and
- one or more control inputs for receiving at least a subset of selection signals from the protection controller;
- wherein the selection signals are configured to select the first CML buffer or the second CML buffer to process the one or more input signals based on the determined common mode voltage.
A method for receiving one or more input signals by a receiver, comprising:
- generating a reference voltage according to a protocol for the one or more input signals;
- comparing a predefined voltage and the reference voltage to determine a common mode voltage;
- generating one or more selection signals based on the common mode voltage;
- selecting a first current mode logic (CML) buffer or a second CML buffer based on the one or more selection signals, the first CML buffer or the second CML buffer selected to process one or more input signals based on the determined common mode voltage, the first CML buffer configured to receive the one or more input signals and at least a subset of the one or more selection signals, and the second CML buffer configured to receive the one or more input signals, one or more output signals from the first CML, and at least a subset of the one or more selection signals.
A double data rate (“DDR”) receiver for receiving at least one input signal comprising:
- a comparator for comparing a reference voltage and a predefined voltage to determine a common mode voltage;
- a protection controller coupled to the comparator, the protection controller configured to generate one or more selection signals based on an output of the comparator;
- and
- a two-stage current mode logic (“CML”) buffer, comprising:
- a first CML buffer comprising:
- one or more inputs for receiving the one or more input signals, and
- one or more control inputs for receiving at least a subset of selection signals from the protection controller;
- and
- a second CML buffer coupled to the first CML, the second CML comprising:
- a first set of inputs for receiving the one or more input signals,
- a second set of inputs for receiving one or more output signals from the first CML buffer, and
- one or more control inputs for receiving at least a subset of selection signals from the protection controller, the selection signals configured to select the first CML buffer or the second CML buffer to process the one or more input signals.
Dependencies are inferred from the claim text.