Clocking circuit and method for time-interleaved analog-to-digital converters

A time-interleaved analog-to-digital converter (ADC), comprising:

• a plurality of ADCs configured to receive an analog input signal, each ADC configured to sample the analog input signal upon receipt of a respective clock signal;
• an open-loop clocking circuit comprising a plurality of clock dividers arranged in a tree architecture, wherein the open-loop clocking circuit is configured to receive a main clock signal having a reference frequency, the open-loop clocking circuit further configured to:
• divide the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal, of the sequential plurality of respective clock signals, starting from the main clock signal, and
• distribute the sequential plurality of respective clock signals to the plurality of ADCs;
• and
• a time-multiplexing circuit coupled to the plurality of ADCs and configured to combine respective digital output signals from the plurality of ADCs into a time series.