Clock data recovery circuit

A clock data recovery circuit, comprising:

• a bit stream data rate divider configured to receive a serial data stream and divide a frequency of the serial data stream by a designated division factor to generate a divided serial data stream having a data rate that is proportionally less than a data rate of the serial data stream;
• and
• a digital phase-locked loop including:
• a Hogge phase detector configured to compare a phase of the divided serial data stream with a phase of a feedback signal within the digital phase-locked loop and output an UP signal associated with phase lagging and a DOWN signal associated with phase leading of the feedback signal versus the divided serial data stream as doublets of sequentially correlated UP/DOWN pulses, wherein for each doublet:
• the UP signal includes a pulse generated responsive to a change in state of the divided serial data stream and a reset responsive to a next rising edge of the feedback signal following that change in state of the divided serial data stream;
• and
• the DOWN signal includes a pulse generated responsive to the reset of the pulse included in the UP signal and a reset responsive to a next falling edge of the feedback signal following the reset of the pulse included in the UP signal;
• an UP time-to-digital converter configured to digitize a duration of the UP signal to generate a digitized-UP signal that is registered responsive to termination of the UP signal;
• a DOWN time-to-digital converter configured to digitize a duration of the DOWN signal to generate a digitized-DOWN signal that is registered responsive to termination of the DOWN signal;
• a subtractor configured to output a signal representing a digital difference between the digitized-UP signal and the digitized-DOWN signal;
• a digital loop filter configured to filter the digital difference signal to generate a filtered signal;
• a digitally controlled oscillator configured to output a clock signal having a phase that is based on the filtered signal;
• and
• a feedback divider configured to divide the clock signal according to a designated feedback division factor to generate the feedback signal such that the feedback signal has a same frequency as the data rate of the divided serial data stream.

A clock data recovery method, comprising:

• receiving a serial data stream;
• dividing the serial data stream by a designated division factor to generate a divided serial data stream having a data rate that is proportionally less than a data rate of the serial data stream;
• providing the divided serial data stream as input to a digital phase-locked loop comprising a linear phase detector, an UP time-to-digital converter, a DOWN time-to-digital converter, a subtractor, a digital loop filter, a digitally controlled oscillator, and a feedback divider;
• comparing, with the linear phase detector, a phase of the divided serial data stream with a phase of a feedback signal of the digital phase-locked loop to generate an UP signal associated with phase lagging and a DOWN signal associated with phase leading of the feedback signal versus the divided serial data stream;
• digitizing, with the UP time-to-digital converter, a duration of the UP signal to generate a digitized-UP signal;
• digitizing, with the DOWN time-to-digital converter, a duration of the DOWN signal to generate a digitized-DOWN signal;
• generating, with the subtractor, a signal representing a digital difference of the digitized-UP signal and the digitized-DOWN signal;
• filtering, with the digital loop filter, the signal representing a digital difference of the digitized-UP signal and the digitized-DOWN signal to generate a filtered signal;
• generating, with the digitally controlled oscillator, a clock signal having a phase that is based on the filtered signal;
• and
• dividing, with the feedback divider, the clock signal according to a designated feedback division factor to generate the feedback signal such that the feedback signal has a same frequency as the data rate of the divided serial data stream.