Application specific integrated circuit accelerators
AssigneeX Development LLC
InventorsMichial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
Life of this patent
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Abstract
An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.
Claims26
An application specific integrated circuit (ASIC) chip comprising:
- a systolic array of cells;
- and
- a plurality of controllable bus lines configured to convey data among the systolic array of cells,
- wherein the systolic array of cells is arranged in a plurality of tiles, each tile of the plurality of tiles comprising 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the plurality of controllable bus lines, and 3) a corresponding local memory coupled to each cell of the corresponding subarray of cells of the tile,
- wherein, for each tile of the plurality of tiles,
- the corresponding subset of controllable bus lines comprises a first group of controllable bus lines extending along a first direction and couplable to the corresponding local memory of the tile, each controllable bus line within the first group comprising one or more control elements configured to allow data conveyed over the controllable bus line of the first group to skip the tile, and
- the corresponding subset of controllable bus lines comprises a second group of controllable bus lines extending along a second direction, different from the first direction, and couplable to the subarray of cells of the tile, each controllable bus line within the second group comprising one or more control elements configured to allow data conveyed over the controllable bus line of the second group to skip the tile;
- wherein the ASIC chip further comprises:
- a communication interface;
- and
- a vector processing unit configured to receive outputs from the plurality of tiles and to compute vector computation output values based on the outputs received from the plurality of tiles,
- wherein the plurality of controllable bus lines is configured to convey data among the vector processing unit, the communication interface, and the plurality of tiles, and
- wherein a first subset of the plurality of tiles are arranged in a first section on a first side of the vector processing unit, and a second subset of the plurality of tiles are arranged in a second section on a second side of the vector processing unit.
A method of operating an application specific integrated circuit (ASIC) chip comprising a vector processing unit, a plurality of tiles and a plurality of controllable bus lines configured to convey data among the plurality of tiles, wherein the plurality of tiles are arranged in a grid, each tile of the plurality of tiles comprising a corresponding computational array of cells, corresponding local memory coupled to each cell of the computational array of cells of the tile, and a corresponding subset of controllable bus lines of the plurality of controllable bus lines,
- wherein, for each tile of the plurality of tiles,
- the corresponding subset of controllable bus lines comprises a first group of controllable bus lines extending along a first direction and couplable to the corresponding local memory of the tile, each controllable bus line within the first group comprising one or more control elements configured to allow data conveyed over the controllable bus line of the first group to skip the tile, and
- the corresponding subset of controllable bus lines comprises a second group of controllable bus lines extending along a second direction, different from the first direction, and couplable to the computational array of cells of the tile, each controllable bus line within the second group comprising one or more control elements configured to allow data conveyed over the controllable bus line of the second group to skip the tile,
- the method comprising:
- controlling a first subset of controllable bus lines to load associated with a first tile, from the first subset into the corresponding local memory of the first tile, a plurality of weight inputs and a plurality of activation inputs;
- performing, for the first tile, a computation with the computational array of cells of the first tile, using the plurality of weight inputs and the plurality of activation inputs from the corresponding local memory of the first tile, to provide an output;
- and
- controlling a second subset of controllable bus lines associated with a second tile to skip loading at least one weight input, at least one activation input, or at least one weight input and one activation input from the second subset into the second tile,
- wherein a first subset of the plurality of tiles are arranged in a first section on a first side of the vector processing unit, and a second subset of the plurality of tiles are arranged in a second section on a second side of the vector processing unit.
Dependencies are inferred from the claim text.