Data processing apparatus, and data processing method

A data processing method for a data processing apparatus including frequency interleaver circuitry that includes an interleaver memory for writing and reading data, and an address producing portion configured to produce a write address and a read address, and that writes the data to the interleaver memory in accordance with the write address and reads out the data from the interleaver memory in accordance with the read address, thereby carrying out frequency interleave,

• the address producing portion including
• a first pseudo random number generating portion configured to produce a first random bit stream,
• a second pseudo random number generating portion configured to produce a second random bit stream, and
• a bit producing portion configured to alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first random bit stream,
• the data processing method comprising:
• calculating the write address or the read address by obtaining an exclusive-OR between the first random bit stream and the second random bit stream.

A data processing apparatus comprising:

• frequency deinterleaver circuitry that includes a deinterleaver memory for writing and reading data, and an address producing portion configured to produce a write address and a read address, and that writes the data to the deinterleaver memory in accordance with the write address and reads out the data from the deinterleaver memory in accordance with the read address, thereby carrying out frequency deinterleave,
• wherein the address producing portion includes
• a first pseudo random number generating portion configured to produce a first random bit stream,
• a second pseudo random number generating portion configured to produce a second random bit stream,
• a bit producing portion configured to alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first random bit stream, and
• a calculating portion configured to produce the write address or the read address by obtaining an exclusive-OR between the first random bit stream and the second random bit stream.

A data processing method for a data processing apparatus including frequency deinterleaver circuitry that includes a deinterleaver memory for writing and reading data, and an address producing portion configured to produce a write address and a read address, and that writes the data to the deinterleaver memory in accordance with the write address and reads out the data from the deinterleaver memory in accordance with the read address, thereby carrying out frequency deinterleave,

• the address producing portion including
• a first pseudo random number generating portion configured to produce a first random bit stream,
• a second pseudo random number generating portion configured to produce a second random bit stream, and
• a bit producing portion configured to alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first random bit stream,
• the data processing method comprising:
• calculating the write address or the read address by obtaining an exclusive-OR between the first random bit stream and the second random bit stream.